1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2020-2021 NXP
6 #ifndef __LS1088A_QDS_H
7 #define __LS1088A_QDS_H
9 #include "ls1088a_common.h"
11 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
15 #define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
16 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
18 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
19 #define SPD_EEPROM_ADDRESS 0x51
20 #define CONFIG_SYS_SPD_BUS_NUM 0
26 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
27 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
28 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
29 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
31 #define CONFIG_SYS_NOR0_CSPR \
32 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
36 #define CONFIG_SYS_NOR0_CSPR_EARLY \
37 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
41 #define CONFIG_SYS_NOR1_CSPR \
42 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
46 #define CONFIG_SYS_NOR1_CSPR_EARLY \
47 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
51 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
52 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
53 FTIM0_NOR_TEADC(0x5) | \
54 FTIM0_NOR_TAVDS(0x6) | \
56 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
57 FTIM1_NOR_TRAD_NOR(0x1a) | \
58 FTIM1_NOR_TSEQRAD_NOR(0x13))
59 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \
60 FTIM2_NOR_TCH(0x8) | \
61 FTIM2_NOR_TWPH(0xe) | \
63 #define CONFIG_SYS_NOR_FTIM3 0x04000000
64 #define CONFIG_SYS_IFC_CCR 0x01000000
67 #define CONFIG_SYS_FLASH_QUIET_TEST
68 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
70 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
71 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
72 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
74 #define CONFIG_SYS_FLASH_EMPTY_INFO
75 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
76 CONFIG_SYS_FLASH_BASE + 0x40000000}
80 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
81 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
83 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
84 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
85 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
86 | CSPR_MSEL_NAND /* MSEL = NAND */ \
88 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
90 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
91 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
92 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
93 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
94 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
95 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
96 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
98 /* ONFI NAND Flash mode0 Timing Params */
99 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
100 FTIM0_NAND_TWP(0x18) | \
101 FTIM0_NAND_TWCHT(0x07) | \
102 FTIM0_NAND_TWH(0x0a))
103 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
104 FTIM1_NAND_TWBE(0x39) | \
105 FTIM1_NAND_TRR(0x0e) | \
106 FTIM1_NAND_TRP(0x18))
107 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
108 FTIM2_NAND_TREH(0x0a) | \
109 FTIM2_NAND_TWHRE(0x1e))
110 #define CONFIG_SYS_NAND_FTIM3 0x0
112 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
113 #define CONFIG_SYS_MAX_NAND_DEVICE 1
114 #define CONFIG_MTD_NAND_VERIFY_WRITE
116 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
117 #define QIXIS_LBMAP_SWITCH 6
118 #define QIXIS_QMAP_MASK 0xe0
119 #define QIXIS_QMAP_SHIFT 5
120 #define QIXIS_LBMAP_MASK 0x0f
121 #define QIXIS_LBMAP_SHIFT 0
122 #define QIXIS_LBMAP_DFLTBANK 0x0e
123 #define QIXIS_LBMAP_ALTBANK 0x2e
124 #define QIXIS_LBMAP_SD 0x00
125 #define QIXIS_LBMAP_EMMC 0x00
126 #define QIXIS_LBMAP_IFC 0x00
127 #define QIXIS_LBMAP_SD_QSPI 0x0e
128 #define QIXIS_LBMAP_QSPI 0x0e
129 #define QIXIS_RCW_SRC_IFC 0x25
130 #define QIXIS_RCW_SRC_SD 0x40
131 #define QIXIS_RCW_SRC_EMMC 0x41
132 #define QIXIS_RCW_SRC_QSPI 0x62
133 #define QIXIS_RST_CTL_RESET 0x41
134 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
135 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
136 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
137 #define QIXIS_RST_FORCE_MEM 0x01
138 #define QIXIS_STAT_PRES1 0xb
139 #define QIXIS_SDID_MASK 0x07
140 #define QIXIS_ESDHC_NO_ADAPTER 0x7
142 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
143 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
147 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
152 #define SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
153 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
154 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
156 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12)
158 /* QIXIS Timing parameters*/
159 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
160 FTIM0_GPCM_TEADC(0x0e) | \
161 FTIM0_GPCM_TEAHC(0x0e))
162 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
163 FTIM1_GPCM_TRAD(0x3f))
164 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
165 FTIM2_GPCM_TCH(0xf) | \
166 FTIM2_GPCM_TWP(0x3E))
167 #define SYS_FPGA_CS_FTIM3 0x0
169 #ifdef CONFIG_TFABOOT
170 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
171 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
172 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
173 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
174 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
175 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
176 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
177 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
178 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
179 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
180 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
181 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
182 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
183 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
184 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
185 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
186 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
187 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
188 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
189 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
190 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
191 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
192 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
193 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
194 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
195 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
196 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
197 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
198 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
199 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
200 #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
201 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
202 #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
203 #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
204 #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
205 #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
207 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
208 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
209 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
210 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
211 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
212 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
213 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
214 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
215 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
216 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
217 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
218 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
219 #define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK
220 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
221 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
222 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
223 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
224 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
226 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
227 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
228 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
229 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
230 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
231 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
232 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
233 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
234 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
235 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
236 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
237 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
238 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
239 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
240 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
241 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
242 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
243 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
244 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
245 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
246 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
247 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
248 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
249 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
250 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
251 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
252 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
253 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
254 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
255 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
256 #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
257 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
258 #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
259 #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
260 #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
261 #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
265 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
268 * I2C bus multiplexer
270 #define I2C_MUX_PCA_ADDR_PRI 0x77
271 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
272 #define I2C_RETIMER_ADDR 0x18
273 #define I2C_RETIMER_ADDR2 0x19
274 #define I2C_MUX_CH_DEFAULT 0x8
275 #define I2C_MUX_CH5 0xD
277 #define I2C_MUX_CH_VOL_MONITOR 0xA
279 /* Voltage monitor on channel 2*/
280 #define I2C_VOL_MONITOR_ADDR 0x63
281 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
282 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
283 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
284 #define I2C_SVDD_MONITOR_ADDR 0x4F
286 /* The lowest and highest voltage allowed for LS1088AQDS */
287 #define VDD_MV_MIN 819
288 #define VDD_MV_MAX 1212
290 #define PWM_CHANNEL0 0x0
296 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
299 #define CONFIG_SYS_I2C_EEPROM_NXID
300 #define CONFIG_SYS_EEPROM_BUS_NUM 0
302 #ifdef CONFIG_FSL_DSPI
303 #if !defined(CONFIG_TFABOOT) && \
304 !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
308 #define CONFIG_FSL_MEMAC
311 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
312 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
315 "kernelheader_addr_r=0x80200000\0" \
316 "fdtheader_addr_r=0x80100000\0" \
317 "kernel_addr_r=0x81000000\0" \
318 "fdt_addr_r=0x90000000\0" \
319 "load_addr=0xa0000000\0"
321 /* Initial environment variables */
322 #ifdef CONFIG_NXP_ESBC
323 #undef CONFIG_EXTRA_ENV_SETTINGS
324 #define CONFIG_EXTRA_ENV_SETTINGS \
326 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
327 "loadaddr=0x90100000\0" \
328 "kernel_addr=0x100000\0" \
329 "ramdisk_addr=0x800000\0" \
330 "ramdisk_size=0x2000000\0" \
331 "fdt_high=0xa0000000\0" \
332 "initrd_high=0xffffffffffffffff\0" \
333 "kernel_start=0x1000000\0" \
334 "kernel_load=0xa0000000\0" \
335 "kernel_size=0x2800000\0" \
336 "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x200000;" \
337 "sf read 0xa0640000 0x640000 0x4000; esbc_validate 0xa0640000;" \
338 "sf read 0xa0e00000 0xe00000 0x100000;" \
339 "sf read 0xa0680000 0x680000 0x4000;esbc_validate 0xa0680000;" \
340 "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \
341 "mcmemsize=0x70000000 \0"
342 #else /* if !(CONFIG_NXP_ESBC) */
343 #ifdef CONFIG_TFABOOT
344 #define QSPI_MC_INIT_CMD \
345 "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
346 "sf read 0x80e00000 0xE00000 0x100000;" \
347 "fsl_mc start mc 0x80a00000 0x80e00000\0"
348 #define SD_MC_INIT_CMD \
349 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
350 "mmc read 0x80e00000 0x7000 0x800;" \
351 "fsl_mc start mc 0x80a00000 0x80e00000\0"
352 #define IFC_MC_INIT_CMD \
353 "fsl_mc start mc 0x580A00000 0x580E00000\0"
355 #undef CONFIG_EXTRA_ENV_SETTINGS
356 #define CONFIG_EXTRA_ENV_SETTINGS \
358 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
359 "loadaddr=0x90100000\0" \
360 "kernel_addr=0x100000\0" \
361 "kernel_addr_sd=0x800\0" \
362 "ramdisk_addr=0x800000\0" \
363 "ramdisk_size=0x2000000\0" \
364 "fdt_high=0xa0000000\0" \
365 "initrd_high=0xffffffffffffffff\0" \
366 "kernel_start=0x1000000\0" \
367 "kernel_start_sd=0x8000\0" \
368 "kernel_load=0xa0000000\0" \
369 "kernel_size=0x2800000\0" \
370 "kernel_size_sd=0x14000\0" \
371 "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
372 "sf read 0x80e00000 0xE00000 0x100000;" \
373 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
374 "mcmemsize=0x70000000 \0" \
375 "BOARD=ls1088aqds\0" \
376 "scriptaddr=0x80000000\0" \
377 "scripthdraddr=0x80080000\0" \
379 "boot_scripts=ls1088aqds_boot.scr\0" \
380 "boot_script_hdr=hdr_ls1088aqds_bs.out\0" \
381 "scan_dev_for_boot_part=" \
382 "part list ${devtype} ${devnum} devplist; " \
383 "env exists devplist || setenv devplist 1; " \
384 "for distro_bootpart in ${devplist}; do " \
385 "if fstype ${devtype} " \
386 "${devnum}:${distro_bootpart} " \
387 "bootfstype; then " \
388 "run scan_dev_for_boot; " \
392 "load ${devtype} ${devnum}:${distro_bootpart} " \
393 "${scriptaddr} ${prefix}${script}; " \
394 "env exists secureboot && load ${devtype} " \
395 "${devnum}:${distro_bootpart} " \
396 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
397 "env exists secureboot " \
398 "&& esbc_validate ${scripthdraddr};" \
399 "source ${scriptaddr}\0" \
400 "qspi_bootcmd=echo Trying load from qspi..; " \
402 "sf read 0x80001000 0xd00000 0x100000; " \
403 "fsl_mc lazyapply dpl 0x80001000 && " \
404 "sf read $kernel_load $kernel_start " \
405 "$kernel_size && bootm $kernel_load#$BOARD\0" \
406 "sd_bootcmd=echo Trying load from sd card..; " \
407 "mmcinfo;mmc read 0x80001000 0x6800 0x800; "\
408 "fsl_mc lazyapply dpl 0x80001000 && " \
409 "mmc read $kernel_load $kernel_start_sd " \
410 "$kernel_size_sd && bootm $kernel_load#$BOARD\0" \
411 "nor_bootcmd=echo Trying load from nor..; " \
412 "fsl_mc lazyapply dpl 0x580d00000 && " \
413 "cp.b $kernel_start $kernel_load " \
414 "$kernel_size && bootm $kernel_load#$BOARD\0"
416 #if defined(CONFIG_QSPI_BOOT)
417 #undef CONFIG_EXTRA_ENV_SETTINGS
418 #define CONFIG_EXTRA_ENV_SETTINGS \
420 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
421 "loadaddr=0x90100000\0" \
422 "kernel_addr=0x100000\0" \
423 "ramdisk_addr=0x800000\0" \
424 "ramdisk_size=0x2000000\0" \
425 "fdt_high=0xa0000000\0" \
426 "initrd_high=0xffffffffffffffff\0" \
427 "kernel_start=0x1000000\0" \
428 "kernel_load=0xa0000000\0" \
429 "kernel_size=0x2800000\0" \
430 "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
431 "sf read 0x80e00000 0xE00000 0x100000;" \
432 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
433 "mcmemsize=0x70000000 \0"
434 #elif defined(CONFIG_SD_BOOT)
435 #undef CONFIG_EXTRA_ENV_SETTINGS
436 #define CONFIG_EXTRA_ENV_SETTINGS \
438 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
439 "loadaddr=0x90100000\0" \
440 "kernel_addr=0x800\0" \
441 "ramdisk_addr=0x800000\0" \
442 "ramdisk_size=0x2000000\0" \
443 "fdt_high=0xa0000000\0" \
444 "initrd_high=0xffffffffffffffff\0" \
445 "kernel_start=0x8000\0" \
446 "kernel_load=0xa0000000\0" \
447 "kernel_size=0x14000\0" \
448 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
449 "mmc read 0x80e00000 0x7000 0x800;" \
450 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
451 "mcmemsize=0x70000000 \0"
453 #undef CONFIG_EXTRA_ENV_SETTINGS
454 #define CONFIG_EXTRA_ENV_SETTINGS \
456 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
457 "loadaddr=0x90100000\0" \
458 "kernel_addr=0x100000\0" \
459 "ramdisk_addr=0x800000\0" \
460 "ramdisk_size=0x2000000\0" \
461 "fdt_high=0xa0000000\0" \
462 "initrd_high=0xffffffffffffffff\0" \
463 "kernel_start=0x1000000\0" \
464 "kernel_load=0xa0000000\0" \
465 "kernel_size=0x2800000\0" \
466 "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \
467 "mcmemsize=0x70000000 \0"
469 #endif /* CONFIG_TFABOOT */
470 #endif /* CONFIG_NXP_ESBC */
472 #ifdef CONFIG_TFABOOT
473 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
474 "env exists secureboot && esbc_halt;;"
475 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
476 "env exists secureboot && esbc_halt;;"
477 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
478 "env exists secureboot && esbc_halt;;"
481 #ifdef CONFIG_FSL_MC_ENET
482 #define CONFIG_FSL_MEMAC
483 #define RGMII_PHY1_ADDR 0x1
484 #define RGMII_PHY2_ADDR 0x2
485 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
486 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
487 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
488 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
490 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
491 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
492 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
493 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
494 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
495 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
496 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
497 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
498 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
499 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
500 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
501 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
502 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
503 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
504 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
505 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
509 #define BOOT_TARGET_DEVICES(func) \
512 func(SCSI, scsi, 0) \
514 #include <config_distro_bootcmd.h>
516 #include <asm/fsl_secure_boot.h>
518 #endif /* __LS1088A_QDS_H */