1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2020-2021 NXP
6 #ifndef __LS1088A_QDS_H
7 #define __LS1088A_QDS_H
9 #include "ls1088a_common.h"
13 unsigned long get_board_sys_clk(void);
14 unsigned long get_board_ddr_clk(void);
18 #define CONFIG_MISC_INIT_R
21 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
22 #define CONFIG_QIXIS_I2C_ACCESS
25 #define CONFIG_SYS_CLK_FREQ 100000000
26 #define CONFIG_DDR_CLK_FREQ 100000000
28 #define CONFIG_QIXIS_I2C_ACCESS
29 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
30 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
33 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
34 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
36 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
38 #define CONFIG_DDR_SPD
39 #define CONFIG_DDR_ECC
40 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
41 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
42 #define SPD_EEPROM_ADDRESS 0x51
43 #define CONFIG_SYS_SPD_BUS_NUM 0
49 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
50 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
51 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
52 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
54 #define CONFIG_SYS_NOR0_CSPR \
55 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
59 #define CONFIG_SYS_NOR0_CSPR_EARLY \
60 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
64 #define CONFIG_SYS_NOR1_CSPR \
65 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
69 #define CONFIG_SYS_NOR1_CSPR_EARLY \
70 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
74 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
75 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
76 FTIM0_NOR_TEADC(0x5) | \
77 FTIM0_NOR_TAVDS(0x6) | \
79 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
80 FTIM1_NOR_TRAD_NOR(0x1a) | \
81 FTIM1_NOR_TSEQRAD_NOR(0x13))
82 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \
83 FTIM2_NOR_TCH(0x8) | \
84 FTIM2_NOR_TWPH(0xe) | \
86 #define CONFIG_SYS_NOR_FTIM3 0x04000000
87 #define CONFIG_SYS_IFC_CCR 0x01000000
90 #define CONFIG_SYS_FLASH_QUIET_TEST
91 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
93 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
94 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
95 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
96 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
98 #define CONFIG_SYS_FLASH_EMPTY_INFO
99 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
100 CONFIG_SYS_FLASH_BASE + 0x40000000}
104 #define CONFIG_NAND_FSL_IFC
105 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
106 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
108 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
109 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
110 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
111 | CSPR_MSEL_NAND /* MSEL = NAND */ \
113 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
115 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
116 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
117 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
118 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
119 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
120 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
121 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
123 #define CONFIG_SYS_NAND_ONFI_DETECTION
125 /* ONFI NAND Flash mode0 Timing Params */
126 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
127 FTIM0_NAND_TWP(0x18) | \
128 FTIM0_NAND_TWCHT(0x07) | \
129 FTIM0_NAND_TWH(0x0a))
130 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
131 FTIM1_NAND_TWBE(0x39) | \
132 FTIM1_NAND_TRR(0x0e) | \
133 FTIM1_NAND_TRP(0x18))
134 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
135 FTIM2_NAND_TREH(0x0a) | \
136 FTIM2_NAND_TWHRE(0x1e))
137 #define CONFIG_SYS_NAND_FTIM3 0x0
139 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
140 #define CONFIG_SYS_MAX_NAND_DEVICE 1
141 #define CONFIG_MTD_NAND_VERIFY_WRITE
143 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
145 #define CONFIG_FSL_QIXIS
146 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
147 #define QIXIS_LBMAP_SWITCH 6
148 #define QIXIS_QMAP_MASK 0xe0
149 #define QIXIS_QMAP_SHIFT 5
150 #define QIXIS_LBMAP_MASK 0x0f
151 #define QIXIS_LBMAP_SHIFT 0
152 #define QIXIS_LBMAP_DFLTBANK 0x0e
153 #define QIXIS_LBMAP_ALTBANK 0x2e
154 #define QIXIS_LBMAP_SD 0x00
155 #define QIXIS_LBMAP_EMMC 0x00
156 #define QIXIS_LBMAP_IFC 0x00
157 #define QIXIS_LBMAP_SD_QSPI 0x0e
158 #define QIXIS_LBMAP_QSPI 0x0e
159 #define QIXIS_RCW_SRC_IFC 0x25
160 #define QIXIS_RCW_SRC_SD 0x40
161 #define QIXIS_RCW_SRC_EMMC 0x41
162 #define QIXIS_RCW_SRC_QSPI 0x62
163 #define QIXIS_RST_CTL_RESET 0x41
164 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
165 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
166 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
167 #define QIXIS_RST_FORCE_MEM 0x01
168 #define QIXIS_STAT_PRES1 0xb
169 #define QIXIS_SDID_MASK 0x07
170 #define QIXIS_ESDHC_NO_ADAPTER 0x7
172 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
173 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
177 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
182 #define SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
183 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
184 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
186 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12)
188 /* QIXIS Timing parameters*/
189 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
190 FTIM0_GPCM_TEADC(0x0e) | \
191 FTIM0_GPCM_TEAHC(0x0e))
192 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
193 FTIM1_GPCM_TRAD(0x3f))
194 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
195 FTIM2_GPCM_TCH(0xf) | \
196 FTIM2_GPCM_TWP(0x3E))
197 #define SYS_FPGA_CS_FTIM3 0x0
199 #ifdef CONFIG_TFABOOT
200 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
201 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
202 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
203 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
204 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
205 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
206 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
207 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
208 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
209 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
210 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
211 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
212 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
213 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
214 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
215 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
216 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
217 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
218 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
219 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
220 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
221 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
222 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
223 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
224 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
225 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
226 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
227 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
228 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
229 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
230 #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
231 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
232 #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
233 #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
234 #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
235 #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
237 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
238 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
239 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
240 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
241 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
242 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
243 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
244 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
245 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
246 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
247 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
248 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
249 #define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK
250 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
251 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
252 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
253 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
254 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
256 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
257 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
258 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
259 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
260 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
261 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
262 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
263 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
264 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
265 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
266 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
267 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
268 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
269 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
270 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
271 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
272 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
273 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
274 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
275 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
276 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
277 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
278 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
279 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
280 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
281 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
282 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
283 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
284 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
285 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
286 #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
287 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
288 #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
289 #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
290 #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
291 #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
295 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
298 * I2C bus multiplexer
300 #define I2C_MUX_PCA_ADDR_PRI 0x77
301 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
302 #define I2C_RETIMER_ADDR 0x18
303 #define I2C_RETIMER_ADDR2 0x19
304 #define I2C_MUX_CH_DEFAULT 0x8
305 #define I2C_MUX_CH5 0xD
307 #define I2C_MUX_CH_VOL_MONITOR 0xA
309 /* Voltage monitor on channel 2*/
310 #define I2C_VOL_MONITOR_ADDR 0x63
311 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
312 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
313 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
314 #define I2C_SVDD_MONITOR_ADDR 0x4F
316 #define CONFIG_VID_FLS_ENV "ls1088aqds_vdd_mv"
319 /* The lowest and highest voltage allowed for LS1088AQDS */
320 #define VDD_MV_MIN 819
321 #define VDD_MV_MAX 1212
323 #define CONFIG_VOL_MONITOR_LTC3882_SET
324 #define CONFIG_VOL_MONITOR_LTC3882_READ
326 #define PWM_CHANNEL0 0x0
332 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
335 #define CONFIG_SYS_I2C_EEPROM_NXID
336 #define CONFIG_SYS_EEPROM_BUS_NUM 0
338 #ifdef CONFIG_FSL_DSPI
339 #define CONFIG_SPI_FLASH_STMICRO
340 #define CONFIG_SPI_FLASH_SST
341 #define CONFIG_SPI_FLASH_EON
342 #if !defined(CONFIG_TFABOOT) && \
343 !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
347 #ifdef CONFIG_SPL_BUILD
348 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
350 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
353 #define CONFIG_FSL_MEMAC
356 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
357 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
360 "kernelheader_addr_r=0x80200000\0" \
361 "fdtheader_addr_r=0x80100000\0" \
362 "kernel_addr_r=0x81000000\0" \
363 "fdt_addr_r=0x90000000\0" \
364 "load_addr=0xa0000000\0"
366 /* Initial environment variables */
367 #ifdef CONFIG_NXP_ESBC
368 #undef CONFIG_EXTRA_ENV_SETTINGS
369 #define CONFIG_EXTRA_ENV_SETTINGS \
371 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
372 "loadaddr=0x90100000\0" \
373 "kernel_addr=0x100000\0" \
374 "ramdisk_addr=0x800000\0" \
375 "ramdisk_size=0x2000000\0" \
376 "fdt_high=0xa0000000\0" \
377 "initrd_high=0xffffffffffffffff\0" \
378 "kernel_start=0x1000000\0" \
379 "kernel_load=0xa0000000\0" \
380 "kernel_size=0x2800000\0" \
381 "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x200000;" \
382 "sf read 0xa0640000 0x640000 0x4000; esbc_validate 0xa0640000;" \
383 "sf read 0xa0e00000 0xe00000 0x100000;" \
384 "sf read 0xa0680000 0x680000 0x4000;esbc_validate 0xa0680000;" \
385 "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \
386 "mcmemsize=0x70000000 \0"
387 #else /* if !(CONFIG_NXP_ESBC) */
388 #ifdef CONFIG_TFABOOT
389 #define QSPI_MC_INIT_CMD \
390 "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
391 "sf read 0x80e00000 0xE00000 0x100000;" \
392 "fsl_mc start mc 0x80a00000 0x80e00000\0"
393 #define SD_MC_INIT_CMD \
394 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
395 "mmc read 0x80e00000 0x7000 0x800;" \
396 "fsl_mc start mc 0x80a00000 0x80e00000\0"
397 #define IFC_MC_INIT_CMD \
398 "fsl_mc start mc 0x580A00000 0x580E00000\0"
400 #undef CONFIG_EXTRA_ENV_SETTINGS
401 #define CONFIG_EXTRA_ENV_SETTINGS \
403 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
404 "loadaddr=0x90100000\0" \
405 "kernel_addr=0x100000\0" \
406 "kernel_addr_sd=0x800\0" \
407 "ramdisk_addr=0x800000\0" \
408 "ramdisk_size=0x2000000\0" \
409 "fdt_high=0xa0000000\0" \
410 "initrd_high=0xffffffffffffffff\0" \
411 "kernel_start=0x1000000\0" \
412 "kernel_start_sd=0x8000\0" \
413 "kernel_load=0xa0000000\0" \
414 "kernel_size=0x2800000\0" \
415 "kernel_size_sd=0x14000\0" \
416 "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
417 "sf read 0x80e00000 0xE00000 0x100000;" \
418 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
419 "mcmemsize=0x70000000 \0" \
420 "BOARD=ls1088aqds\0" \
421 "scriptaddr=0x80000000\0" \
422 "scripthdraddr=0x80080000\0" \
424 "boot_scripts=ls1088aqds_boot.scr\0" \
425 "boot_script_hdr=hdr_ls1088aqds_bs.out\0" \
426 "scan_dev_for_boot_part=" \
427 "part list ${devtype} ${devnum} devplist; " \
428 "env exists devplist || setenv devplist 1; " \
429 "for distro_bootpart in ${devplist}; do " \
430 "if fstype ${devtype} " \
431 "${devnum}:${distro_bootpart} " \
432 "bootfstype; then " \
433 "run scan_dev_for_boot; " \
437 "load ${devtype} ${devnum}:${distro_bootpart} " \
438 "${scriptaddr} ${prefix}${script}; " \
439 "env exists secureboot && load ${devtype} " \
440 "${devnum}:${distro_bootpart} " \
441 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
442 "env exists secureboot " \
443 "&& esbc_validate ${scripthdraddr};" \
444 "source ${scriptaddr}\0" \
445 "qspi_bootcmd=echo Trying load from qspi..; " \
447 "sf read 0x80001000 0xd00000 0x100000; " \
448 "fsl_mc lazyapply dpl 0x80001000 && " \
449 "sf read $kernel_load $kernel_start " \
450 "$kernel_size && bootm $kernel_load#$BOARD\0" \
451 "sd_bootcmd=echo Trying load from sd card..; " \
452 "mmcinfo;mmc read 0x80001000 0x6800 0x800; "\
453 "fsl_mc lazyapply dpl 0x80001000 && " \
454 "mmc read $kernel_load $kernel_start_sd " \
455 "$kernel_size_sd && bootm $kernel_load#$BOARD\0" \
456 "nor_bootcmd=echo Trying load from nor..; " \
457 "fsl_mc lazyapply dpl 0x580d00000 && " \
458 "cp.b $kernel_start $kernel_load " \
459 "$kernel_size && bootm $kernel_load#$BOARD\0"
461 #if defined(CONFIG_QSPI_BOOT)
462 #undef CONFIG_EXTRA_ENV_SETTINGS
463 #define CONFIG_EXTRA_ENV_SETTINGS \
465 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
466 "loadaddr=0x90100000\0" \
467 "kernel_addr=0x100000\0" \
468 "ramdisk_addr=0x800000\0" \
469 "ramdisk_size=0x2000000\0" \
470 "fdt_high=0xa0000000\0" \
471 "initrd_high=0xffffffffffffffff\0" \
472 "kernel_start=0x1000000\0" \
473 "kernel_load=0xa0000000\0" \
474 "kernel_size=0x2800000\0" \
475 "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
476 "sf read 0x80e00000 0xE00000 0x100000;" \
477 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
478 "mcmemsize=0x70000000 \0"
479 #elif defined(CONFIG_SD_BOOT)
480 #undef CONFIG_EXTRA_ENV_SETTINGS
481 #define CONFIG_EXTRA_ENV_SETTINGS \
483 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
484 "loadaddr=0x90100000\0" \
485 "kernel_addr=0x800\0" \
486 "ramdisk_addr=0x800000\0" \
487 "ramdisk_size=0x2000000\0" \
488 "fdt_high=0xa0000000\0" \
489 "initrd_high=0xffffffffffffffff\0" \
490 "kernel_start=0x8000\0" \
491 "kernel_load=0xa0000000\0" \
492 "kernel_size=0x14000\0" \
493 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
494 "mmc read 0x80e00000 0x7000 0x800;" \
495 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
496 "mcmemsize=0x70000000 \0"
498 #undef CONFIG_EXTRA_ENV_SETTINGS
499 #define CONFIG_EXTRA_ENV_SETTINGS \
501 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
502 "loadaddr=0x90100000\0" \
503 "kernel_addr=0x100000\0" \
504 "ramdisk_addr=0x800000\0" \
505 "ramdisk_size=0x2000000\0" \
506 "fdt_high=0xa0000000\0" \
507 "initrd_high=0xffffffffffffffff\0" \
508 "kernel_start=0x1000000\0" \
509 "kernel_load=0xa0000000\0" \
510 "kernel_size=0x2800000\0" \
511 "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \
512 "mcmemsize=0x70000000 \0"
514 #endif /* CONFIG_TFABOOT */
515 #endif /* CONFIG_NXP_ESBC */
517 #ifdef CONFIG_TFABOOT
518 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
519 "env exists secureboot && esbc_halt;;"
520 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
521 "env exists secureboot && esbc_halt;;"
522 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
523 "env exists secureboot && esbc_halt;;"
526 #ifdef CONFIG_FSL_MC_ENET
527 #define CONFIG_FSL_MEMAC
528 #define RGMII_PHY1_ADDR 0x1
529 #define RGMII_PHY2_ADDR 0x2
530 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
531 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
532 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
533 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
535 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
536 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
537 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
538 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
539 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
540 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
541 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
542 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
543 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
544 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
545 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
546 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
547 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
548 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
549 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
550 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
552 #define CONFIG_ETHPRIME "DPMAC1@xgmii"
553 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
557 #define BOOT_TARGET_DEVICES(func) \
560 func(SCSI, scsi, 0) \
562 #include <config_distro_bootcmd.h>
564 #include <asm/fsl_secure_boot.h>
566 #endif /* __LS1088A_QDS_H */