1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2020-2021 NXP
6 #ifndef __LS1088A_QDS_H
7 #define __LS1088A_QDS_H
9 #include "ls1088a_common.h"
11 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
12 #define CONFIG_QIXIS_I2C_ACCESS
15 #define CONFIG_QIXIS_I2C_ACCESS
18 #define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
19 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
21 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
22 #define SPD_EEPROM_ADDRESS 0x51
23 #define CONFIG_SYS_SPD_BUS_NUM 0
29 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
30 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
31 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
32 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
34 #define CONFIG_SYS_NOR0_CSPR \
35 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
39 #define CONFIG_SYS_NOR0_CSPR_EARLY \
40 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
44 #define CONFIG_SYS_NOR1_CSPR \
45 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
49 #define CONFIG_SYS_NOR1_CSPR_EARLY \
50 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
54 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
55 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
56 FTIM0_NOR_TEADC(0x5) | \
57 FTIM0_NOR_TAVDS(0x6) | \
59 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
60 FTIM1_NOR_TRAD_NOR(0x1a) | \
61 FTIM1_NOR_TSEQRAD_NOR(0x13))
62 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \
63 FTIM2_NOR_TCH(0x8) | \
64 FTIM2_NOR_TWPH(0xe) | \
66 #define CONFIG_SYS_NOR_FTIM3 0x04000000
67 #define CONFIG_SYS_IFC_CCR 0x01000000
70 #define CONFIG_SYS_FLASH_QUIET_TEST
71 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
73 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
74 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
75 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
77 #define CONFIG_SYS_FLASH_EMPTY_INFO
78 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
79 CONFIG_SYS_FLASH_BASE + 0x40000000}
83 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
84 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
86 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
87 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
88 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
89 | CSPR_MSEL_NAND /* MSEL = NAND */ \
91 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
93 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
94 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
95 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
96 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
97 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
98 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
99 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
101 /* ONFI NAND Flash mode0 Timing Params */
102 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
103 FTIM0_NAND_TWP(0x18) | \
104 FTIM0_NAND_TWCHT(0x07) | \
105 FTIM0_NAND_TWH(0x0a))
106 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
107 FTIM1_NAND_TWBE(0x39) | \
108 FTIM1_NAND_TRR(0x0e) | \
109 FTIM1_NAND_TRP(0x18))
110 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
111 FTIM2_NAND_TREH(0x0a) | \
112 FTIM2_NAND_TWHRE(0x1e))
113 #define CONFIG_SYS_NAND_FTIM3 0x0
115 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
116 #define CONFIG_SYS_MAX_NAND_DEVICE 1
117 #define CONFIG_MTD_NAND_VERIFY_WRITE
119 #define CONFIG_FSL_QIXIS
120 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
121 #define QIXIS_LBMAP_SWITCH 6
122 #define QIXIS_QMAP_MASK 0xe0
123 #define QIXIS_QMAP_SHIFT 5
124 #define QIXIS_LBMAP_MASK 0x0f
125 #define QIXIS_LBMAP_SHIFT 0
126 #define QIXIS_LBMAP_DFLTBANK 0x0e
127 #define QIXIS_LBMAP_ALTBANK 0x2e
128 #define QIXIS_LBMAP_SD 0x00
129 #define QIXIS_LBMAP_EMMC 0x00
130 #define QIXIS_LBMAP_IFC 0x00
131 #define QIXIS_LBMAP_SD_QSPI 0x0e
132 #define QIXIS_LBMAP_QSPI 0x0e
133 #define QIXIS_RCW_SRC_IFC 0x25
134 #define QIXIS_RCW_SRC_SD 0x40
135 #define QIXIS_RCW_SRC_EMMC 0x41
136 #define QIXIS_RCW_SRC_QSPI 0x62
137 #define QIXIS_RST_CTL_RESET 0x41
138 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
139 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
140 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
141 #define QIXIS_RST_FORCE_MEM 0x01
142 #define QIXIS_STAT_PRES1 0xb
143 #define QIXIS_SDID_MASK 0x07
144 #define QIXIS_ESDHC_NO_ADAPTER 0x7
146 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
147 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
151 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
156 #define SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
157 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
158 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
160 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12)
162 /* QIXIS Timing parameters*/
163 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
164 FTIM0_GPCM_TEADC(0x0e) | \
165 FTIM0_GPCM_TEAHC(0x0e))
166 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
167 FTIM1_GPCM_TRAD(0x3f))
168 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
169 FTIM2_GPCM_TCH(0xf) | \
170 FTIM2_GPCM_TWP(0x3E))
171 #define SYS_FPGA_CS_FTIM3 0x0
173 #ifdef CONFIG_TFABOOT
174 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
175 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
176 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
177 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
178 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
179 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
180 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
181 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
182 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
183 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
184 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
185 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
186 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
187 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
188 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
189 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
190 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
191 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
192 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
193 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
194 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
195 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
196 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
197 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
198 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
199 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
200 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
201 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
202 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
203 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
204 #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
205 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
206 #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
207 #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
208 #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
209 #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
211 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
212 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
213 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
214 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
215 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
216 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
217 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
218 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
219 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
220 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
221 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
222 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
223 #define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK
224 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
225 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
226 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
227 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
228 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
230 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
231 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
232 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
233 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
234 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
235 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
236 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
237 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
238 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
239 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
240 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
241 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
242 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
243 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
244 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
245 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
246 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
247 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
248 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
249 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
250 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
251 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
252 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
253 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
254 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
255 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
256 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
257 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
258 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
259 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
260 #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
261 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
262 #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
263 #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
264 #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
265 #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
269 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
272 * I2C bus multiplexer
274 #define I2C_MUX_PCA_ADDR_PRI 0x77
275 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
276 #define I2C_RETIMER_ADDR 0x18
277 #define I2C_RETIMER_ADDR2 0x19
278 #define I2C_MUX_CH_DEFAULT 0x8
279 #define I2C_MUX_CH5 0xD
281 #define I2C_MUX_CH_VOL_MONITOR 0xA
283 /* Voltage monitor on channel 2*/
284 #define I2C_VOL_MONITOR_ADDR 0x63
285 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
286 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
287 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
288 #define I2C_SVDD_MONITOR_ADDR 0x4F
290 /* The lowest and highest voltage allowed for LS1088AQDS */
291 #define VDD_MV_MIN 819
292 #define VDD_MV_MAX 1212
294 #define PWM_CHANNEL0 0x0
300 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
303 #define CONFIG_SYS_I2C_EEPROM_NXID
304 #define CONFIG_SYS_EEPROM_BUS_NUM 0
306 #ifdef CONFIG_FSL_DSPI
307 #if !defined(CONFIG_TFABOOT) && \
308 !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
312 #define CONFIG_FSL_MEMAC
315 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
316 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
319 "kernelheader_addr_r=0x80200000\0" \
320 "fdtheader_addr_r=0x80100000\0" \
321 "kernel_addr_r=0x81000000\0" \
322 "fdt_addr_r=0x90000000\0" \
323 "load_addr=0xa0000000\0"
325 /* Initial environment variables */
326 #ifdef CONFIG_NXP_ESBC
327 #undef CONFIG_EXTRA_ENV_SETTINGS
328 #define CONFIG_EXTRA_ENV_SETTINGS \
330 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
331 "loadaddr=0x90100000\0" \
332 "kernel_addr=0x100000\0" \
333 "ramdisk_addr=0x800000\0" \
334 "ramdisk_size=0x2000000\0" \
335 "fdt_high=0xa0000000\0" \
336 "initrd_high=0xffffffffffffffff\0" \
337 "kernel_start=0x1000000\0" \
338 "kernel_load=0xa0000000\0" \
339 "kernel_size=0x2800000\0" \
340 "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x200000;" \
341 "sf read 0xa0640000 0x640000 0x4000; esbc_validate 0xa0640000;" \
342 "sf read 0xa0e00000 0xe00000 0x100000;" \
343 "sf read 0xa0680000 0x680000 0x4000;esbc_validate 0xa0680000;" \
344 "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \
345 "mcmemsize=0x70000000 \0"
346 #else /* if !(CONFIG_NXP_ESBC) */
347 #ifdef CONFIG_TFABOOT
348 #define QSPI_MC_INIT_CMD \
349 "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
350 "sf read 0x80e00000 0xE00000 0x100000;" \
351 "fsl_mc start mc 0x80a00000 0x80e00000\0"
352 #define SD_MC_INIT_CMD \
353 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
354 "mmc read 0x80e00000 0x7000 0x800;" \
355 "fsl_mc start mc 0x80a00000 0x80e00000\0"
356 #define IFC_MC_INIT_CMD \
357 "fsl_mc start mc 0x580A00000 0x580E00000\0"
359 #undef CONFIG_EXTRA_ENV_SETTINGS
360 #define CONFIG_EXTRA_ENV_SETTINGS \
362 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
363 "loadaddr=0x90100000\0" \
364 "kernel_addr=0x100000\0" \
365 "kernel_addr_sd=0x800\0" \
366 "ramdisk_addr=0x800000\0" \
367 "ramdisk_size=0x2000000\0" \
368 "fdt_high=0xa0000000\0" \
369 "initrd_high=0xffffffffffffffff\0" \
370 "kernel_start=0x1000000\0" \
371 "kernel_start_sd=0x8000\0" \
372 "kernel_load=0xa0000000\0" \
373 "kernel_size=0x2800000\0" \
374 "kernel_size_sd=0x14000\0" \
375 "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
376 "sf read 0x80e00000 0xE00000 0x100000;" \
377 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
378 "mcmemsize=0x70000000 \0" \
379 "BOARD=ls1088aqds\0" \
380 "scriptaddr=0x80000000\0" \
381 "scripthdraddr=0x80080000\0" \
383 "boot_scripts=ls1088aqds_boot.scr\0" \
384 "boot_script_hdr=hdr_ls1088aqds_bs.out\0" \
385 "scan_dev_for_boot_part=" \
386 "part list ${devtype} ${devnum} devplist; " \
387 "env exists devplist || setenv devplist 1; " \
388 "for distro_bootpart in ${devplist}; do " \
389 "if fstype ${devtype} " \
390 "${devnum}:${distro_bootpart} " \
391 "bootfstype; then " \
392 "run scan_dev_for_boot; " \
396 "load ${devtype} ${devnum}:${distro_bootpart} " \
397 "${scriptaddr} ${prefix}${script}; " \
398 "env exists secureboot && load ${devtype} " \
399 "${devnum}:${distro_bootpart} " \
400 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
401 "env exists secureboot " \
402 "&& esbc_validate ${scripthdraddr};" \
403 "source ${scriptaddr}\0" \
404 "qspi_bootcmd=echo Trying load from qspi..; " \
406 "sf read 0x80001000 0xd00000 0x100000; " \
407 "fsl_mc lazyapply dpl 0x80001000 && " \
408 "sf read $kernel_load $kernel_start " \
409 "$kernel_size && bootm $kernel_load#$BOARD\0" \
410 "sd_bootcmd=echo Trying load from sd card..; " \
411 "mmcinfo;mmc read 0x80001000 0x6800 0x800; "\
412 "fsl_mc lazyapply dpl 0x80001000 && " \
413 "mmc read $kernel_load $kernel_start_sd " \
414 "$kernel_size_sd && bootm $kernel_load#$BOARD\0" \
415 "nor_bootcmd=echo Trying load from nor..; " \
416 "fsl_mc lazyapply dpl 0x580d00000 && " \
417 "cp.b $kernel_start $kernel_load " \
418 "$kernel_size && bootm $kernel_load#$BOARD\0"
420 #if defined(CONFIG_QSPI_BOOT)
421 #undef CONFIG_EXTRA_ENV_SETTINGS
422 #define CONFIG_EXTRA_ENV_SETTINGS \
424 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
425 "loadaddr=0x90100000\0" \
426 "kernel_addr=0x100000\0" \
427 "ramdisk_addr=0x800000\0" \
428 "ramdisk_size=0x2000000\0" \
429 "fdt_high=0xa0000000\0" \
430 "initrd_high=0xffffffffffffffff\0" \
431 "kernel_start=0x1000000\0" \
432 "kernel_load=0xa0000000\0" \
433 "kernel_size=0x2800000\0" \
434 "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
435 "sf read 0x80e00000 0xE00000 0x100000;" \
436 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
437 "mcmemsize=0x70000000 \0"
438 #elif defined(CONFIG_SD_BOOT)
439 #undef CONFIG_EXTRA_ENV_SETTINGS
440 #define CONFIG_EXTRA_ENV_SETTINGS \
442 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
443 "loadaddr=0x90100000\0" \
444 "kernel_addr=0x800\0" \
445 "ramdisk_addr=0x800000\0" \
446 "ramdisk_size=0x2000000\0" \
447 "fdt_high=0xa0000000\0" \
448 "initrd_high=0xffffffffffffffff\0" \
449 "kernel_start=0x8000\0" \
450 "kernel_load=0xa0000000\0" \
451 "kernel_size=0x14000\0" \
452 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
453 "mmc read 0x80e00000 0x7000 0x800;" \
454 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
455 "mcmemsize=0x70000000 \0"
457 #undef CONFIG_EXTRA_ENV_SETTINGS
458 #define CONFIG_EXTRA_ENV_SETTINGS \
460 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
461 "loadaddr=0x90100000\0" \
462 "kernel_addr=0x100000\0" \
463 "ramdisk_addr=0x800000\0" \
464 "ramdisk_size=0x2000000\0" \
465 "fdt_high=0xa0000000\0" \
466 "initrd_high=0xffffffffffffffff\0" \
467 "kernel_start=0x1000000\0" \
468 "kernel_load=0xa0000000\0" \
469 "kernel_size=0x2800000\0" \
470 "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \
471 "mcmemsize=0x70000000 \0"
473 #endif /* CONFIG_TFABOOT */
474 #endif /* CONFIG_NXP_ESBC */
476 #ifdef CONFIG_TFABOOT
477 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
478 "env exists secureboot && esbc_halt;;"
479 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
480 "env exists secureboot && esbc_halt;;"
481 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
482 "env exists secureboot && esbc_halt;;"
485 #ifdef CONFIG_FSL_MC_ENET
486 #define CONFIG_FSL_MEMAC
487 #define RGMII_PHY1_ADDR 0x1
488 #define RGMII_PHY2_ADDR 0x2
489 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
490 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
491 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
492 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
494 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
495 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
496 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
497 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
498 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
499 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
500 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
501 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
502 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
503 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
504 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
505 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
506 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
507 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
508 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
509 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
513 #define BOOT_TARGET_DEVICES(func) \
516 func(SCSI, scsi, 0) \
518 #include <config_distro_bootcmd.h>
520 #include <asm/fsl_secure_boot.h>
522 #endif /* __LS1088A_QDS_H */