1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2020-2021 NXP
6 #ifndef __LS1088A_QDS_H
7 #define __LS1088A_QDS_H
9 #include "ls1088a_common.h"
11 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
12 #define CONFIG_QIXIS_I2C_ACCESS
15 #define CONFIG_QIXIS_I2C_ACCESS
18 #define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
19 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
21 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
23 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
24 #define SPD_EEPROM_ADDRESS 0x51
25 #define CONFIG_SYS_SPD_BUS_NUM 0
31 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
32 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
33 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
34 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
36 #define CONFIG_SYS_NOR0_CSPR \
37 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
41 #define CONFIG_SYS_NOR0_CSPR_EARLY \
42 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
46 #define CONFIG_SYS_NOR1_CSPR \
47 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
51 #define CONFIG_SYS_NOR1_CSPR_EARLY \
52 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
56 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
57 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
58 FTIM0_NOR_TEADC(0x5) | \
59 FTIM0_NOR_TAVDS(0x6) | \
61 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
62 FTIM1_NOR_TRAD_NOR(0x1a) | \
63 FTIM1_NOR_TSEQRAD_NOR(0x13))
64 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \
65 FTIM2_NOR_TCH(0x8) | \
66 FTIM2_NOR_TWPH(0xe) | \
68 #define CONFIG_SYS_NOR_FTIM3 0x04000000
69 #define CONFIG_SYS_IFC_CCR 0x01000000
72 #define CONFIG_SYS_FLASH_QUIET_TEST
73 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
75 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
76 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
77 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
78 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
80 #define CONFIG_SYS_FLASH_EMPTY_INFO
81 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
82 CONFIG_SYS_FLASH_BASE + 0x40000000}
86 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
87 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
89 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
90 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
91 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
92 | CSPR_MSEL_NAND /* MSEL = NAND */ \
94 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
96 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
97 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
98 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
99 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
100 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
101 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
102 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
104 /* ONFI NAND Flash mode0 Timing Params */
105 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
106 FTIM0_NAND_TWP(0x18) | \
107 FTIM0_NAND_TWCHT(0x07) | \
108 FTIM0_NAND_TWH(0x0a))
109 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
110 FTIM1_NAND_TWBE(0x39) | \
111 FTIM1_NAND_TRR(0x0e) | \
112 FTIM1_NAND_TRP(0x18))
113 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
114 FTIM2_NAND_TREH(0x0a) | \
115 FTIM2_NAND_TWHRE(0x1e))
116 #define CONFIG_SYS_NAND_FTIM3 0x0
118 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
119 #define CONFIG_SYS_MAX_NAND_DEVICE 1
120 #define CONFIG_MTD_NAND_VERIFY_WRITE
122 #define CONFIG_FSL_QIXIS
123 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
124 #define QIXIS_LBMAP_SWITCH 6
125 #define QIXIS_QMAP_MASK 0xe0
126 #define QIXIS_QMAP_SHIFT 5
127 #define QIXIS_LBMAP_MASK 0x0f
128 #define QIXIS_LBMAP_SHIFT 0
129 #define QIXIS_LBMAP_DFLTBANK 0x0e
130 #define QIXIS_LBMAP_ALTBANK 0x2e
131 #define QIXIS_LBMAP_SD 0x00
132 #define QIXIS_LBMAP_EMMC 0x00
133 #define QIXIS_LBMAP_IFC 0x00
134 #define QIXIS_LBMAP_SD_QSPI 0x0e
135 #define QIXIS_LBMAP_QSPI 0x0e
136 #define QIXIS_RCW_SRC_IFC 0x25
137 #define QIXIS_RCW_SRC_SD 0x40
138 #define QIXIS_RCW_SRC_EMMC 0x41
139 #define QIXIS_RCW_SRC_QSPI 0x62
140 #define QIXIS_RST_CTL_RESET 0x41
141 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
142 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
143 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
144 #define QIXIS_RST_FORCE_MEM 0x01
145 #define QIXIS_STAT_PRES1 0xb
146 #define QIXIS_SDID_MASK 0x07
147 #define QIXIS_ESDHC_NO_ADAPTER 0x7
149 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
150 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
154 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
159 #define SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
160 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
161 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
163 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12)
165 /* QIXIS Timing parameters*/
166 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
167 FTIM0_GPCM_TEADC(0x0e) | \
168 FTIM0_GPCM_TEAHC(0x0e))
169 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
170 FTIM1_GPCM_TRAD(0x3f))
171 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
172 FTIM2_GPCM_TCH(0xf) | \
173 FTIM2_GPCM_TWP(0x3E))
174 #define SYS_FPGA_CS_FTIM3 0x0
176 #ifdef CONFIG_TFABOOT
177 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
178 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
179 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
180 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
181 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
182 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
183 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
184 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
185 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
186 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
187 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
188 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
189 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
190 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
191 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
192 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
193 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
194 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
195 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
196 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
197 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
198 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
199 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
200 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
201 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
202 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
203 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
204 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
205 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
206 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
207 #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
208 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
209 #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
210 #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
211 #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
212 #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
214 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
215 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
216 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
217 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
218 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
219 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
220 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
221 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
222 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
223 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
224 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
225 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
226 #define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK
227 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
228 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
229 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
230 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
231 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
233 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
234 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
235 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
236 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
237 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
238 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
239 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
240 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
241 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
242 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
243 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
244 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
245 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
246 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
247 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
248 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
249 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
250 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
251 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
252 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
253 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
254 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
255 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
256 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
257 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
258 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
259 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
260 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
261 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
262 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
263 #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
264 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
265 #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
266 #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
267 #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
268 #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
272 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
275 * I2C bus multiplexer
277 #define I2C_MUX_PCA_ADDR_PRI 0x77
278 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
279 #define I2C_RETIMER_ADDR 0x18
280 #define I2C_RETIMER_ADDR2 0x19
281 #define I2C_MUX_CH_DEFAULT 0x8
282 #define I2C_MUX_CH5 0xD
284 #define I2C_MUX_CH_VOL_MONITOR 0xA
286 /* Voltage monitor on channel 2*/
287 #define I2C_VOL_MONITOR_ADDR 0x63
288 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
289 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
290 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
291 #define I2C_SVDD_MONITOR_ADDR 0x4F
293 /* The lowest and highest voltage allowed for LS1088AQDS */
294 #define VDD_MV_MIN 819
295 #define VDD_MV_MAX 1212
297 #define PWM_CHANNEL0 0x0
303 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
306 #define CONFIG_SYS_I2C_EEPROM_NXID
307 #define CONFIG_SYS_EEPROM_BUS_NUM 0
309 #ifdef CONFIG_FSL_DSPI
310 #if !defined(CONFIG_TFABOOT) && \
311 !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
315 #ifdef CONFIG_SPL_BUILD
316 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
318 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
321 #define CONFIG_FSL_MEMAC
324 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
325 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
328 "kernelheader_addr_r=0x80200000\0" \
329 "fdtheader_addr_r=0x80100000\0" \
330 "kernel_addr_r=0x81000000\0" \
331 "fdt_addr_r=0x90000000\0" \
332 "load_addr=0xa0000000\0"
334 /* Initial environment variables */
335 #ifdef CONFIG_NXP_ESBC
336 #undef CONFIG_EXTRA_ENV_SETTINGS
337 #define CONFIG_EXTRA_ENV_SETTINGS \
339 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
340 "loadaddr=0x90100000\0" \
341 "kernel_addr=0x100000\0" \
342 "ramdisk_addr=0x800000\0" \
343 "ramdisk_size=0x2000000\0" \
344 "fdt_high=0xa0000000\0" \
345 "initrd_high=0xffffffffffffffff\0" \
346 "kernel_start=0x1000000\0" \
347 "kernel_load=0xa0000000\0" \
348 "kernel_size=0x2800000\0" \
349 "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x200000;" \
350 "sf read 0xa0640000 0x640000 0x4000; esbc_validate 0xa0640000;" \
351 "sf read 0xa0e00000 0xe00000 0x100000;" \
352 "sf read 0xa0680000 0x680000 0x4000;esbc_validate 0xa0680000;" \
353 "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \
354 "mcmemsize=0x70000000 \0"
355 #else /* if !(CONFIG_NXP_ESBC) */
356 #ifdef CONFIG_TFABOOT
357 #define QSPI_MC_INIT_CMD \
358 "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
359 "sf read 0x80e00000 0xE00000 0x100000;" \
360 "fsl_mc start mc 0x80a00000 0x80e00000\0"
361 #define SD_MC_INIT_CMD \
362 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
363 "mmc read 0x80e00000 0x7000 0x800;" \
364 "fsl_mc start mc 0x80a00000 0x80e00000\0"
365 #define IFC_MC_INIT_CMD \
366 "fsl_mc start mc 0x580A00000 0x580E00000\0"
368 #undef CONFIG_EXTRA_ENV_SETTINGS
369 #define CONFIG_EXTRA_ENV_SETTINGS \
371 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
372 "loadaddr=0x90100000\0" \
373 "kernel_addr=0x100000\0" \
374 "kernel_addr_sd=0x800\0" \
375 "ramdisk_addr=0x800000\0" \
376 "ramdisk_size=0x2000000\0" \
377 "fdt_high=0xa0000000\0" \
378 "initrd_high=0xffffffffffffffff\0" \
379 "kernel_start=0x1000000\0" \
380 "kernel_start_sd=0x8000\0" \
381 "kernel_load=0xa0000000\0" \
382 "kernel_size=0x2800000\0" \
383 "kernel_size_sd=0x14000\0" \
384 "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
385 "sf read 0x80e00000 0xE00000 0x100000;" \
386 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
387 "mcmemsize=0x70000000 \0" \
388 "BOARD=ls1088aqds\0" \
389 "scriptaddr=0x80000000\0" \
390 "scripthdraddr=0x80080000\0" \
392 "boot_scripts=ls1088aqds_boot.scr\0" \
393 "boot_script_hdr=hdr_ls1088aqds_bs.out\0" \
394 "scan_dev_for_boot_part=" \
395 "part list ${devtype} ${devnum} devplist; " \
396 "env exists devplist || setenv devplist 1; " \
397 "for distro_bootpart in ${devplist}; do " \
398 "if fstype ${devtype} " \
399 "${devnum}:${distro_bootpart} " \
400 "bootfstype; then " \
401 "run scan_dev_for_boot; " \
405 "load ${devtype} ${devnum}:${distro_bootpart} " \
406 "${scriptaddr} ${prefix}${script}; " \
407 "env exists secureboot && load ${devtype} " \
408 "${devnum}:${distro_bootpart} " \
409 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
410 "env exists secureboot " \
411 "&& esbc_validate ${scripthdraddr};" \
412 "source ${scriptaddr}\0" \
413 "qspi_bootcmd=echo Trying load from qspi..; " \
415 "sf read 0x80001000 0xd00000 0x100000; " \
416 "fsl_mc lazyapply dpl 0x80001000 && " \
417 "sf read $kernel_load $kernel_start " \
418 "$kernel_size && bootm $kernel_load#$BOARD\0" \
419 "sd_bootcmd=echo Trying load from sd card..; " \
420 "mmcinfo;mmc read 0x80001000 0x6800 0x800; "\
421 "fsl_mc lazyapply dpl 0x80001000 && " \
422 "mmc read $kernel_load $kernel_start_sd " \
423 "$kernel_size_sd && bootm $kernel_load#$BOARD\0" \
424 "nor_bootcmd=echo Trying load from nor..; " \
425 "fsl_mc lazyapply dpl 0x580d00000 && " \
426 "cp.b $kernel_start $kernel_load " \
427 "$kernel_size && bootm $kernel_load#$BOARD\0"
429 #if defined(CONFIG_QSPI_BOOT)
430 #undef CONFIG_EXTRA_ENV_SETTINGS
431 #define CONFIG_EXTRA_ENV_SETTINGS \
433 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
434 "loadaddr=0x90100000\0" \
435 "kernel_addr=0x100000\0" \
436 "ramdisk_addr=0x800000\0" \
437 "ramdisk_size=0x2000000\0" \
438 "fdt_high=0xa0000000\0" \
439 "initrd_high=0xffffffffffffffff\0" \
440 "kernel_start=0x1000000\0" \
441 "kernel_load=0xa0000000\0" \
442 "kernel_size=0x2800000\0" \
443 "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
444 "sf read 0x80e00000 0xE00000 0x100000;" \
445 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
446 "mcmemsize=0x70000000 \0"
447 #elif defined(CONFIG_SD_BOOT)
448 #undef CONFIG_EXTRA_ENV_SETTINGS
449 #define CONFIG_EXTRA_ENV_SETTINGS \
451 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
452 "loadaddr=0x90100000\0" \
453 "kernel_addr=0x800\0" \
454 "ramdisk_addr=0x800000\0" \
455 "ramdisk_size=0x2000000\0" \
456 "fdt_high=0xa0000000\0" \
457 "initrd_high=0xffffffffffffffff\0" \
458 "kernel_start=0x8000\0" \
459 "kernel_load=0xa0000000\0" \
460 "kernel_size=0x14000\0" \
461 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
462 "mmc read 0x80e00000 0x7000 0x800;" \
463 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
464 "mcmemsize=0x70000000 \0"
466 #undef CONFIG_EXTRA_ENV_SETTINGS
467 #define CONFIG_EXTRA_ENV_SETTINGS \
469 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
470 "loadaddr=0x90100000\0" \
471 "kernel_addr=0x100000\0" \
472 "ramdisk_addr=0x800000\0" \
473 "ramdisk_size=0x2000000\0" \
474 "fdt_high=0xa0000000\0" \
475 "initrd_high=0xffffffffffffffff\0" \
476 "kernel_start=0x1000000\0" \
477 "kernel_load=0xa0000000\0" \
478 "kernel_size=0x2800000\0" \
479 "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \
480 "mcmemsize=0x70000000 \0"
482 #endif /* CONFIG_TFABOOT */
483 #endif /* CONFIG_NXP_ESBC */
485 #ifdef CONFIG_TFABOOT
486 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
487 "env exists secureboot && esbc_halt;;"
488 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
489 "env exists secureboot && esbc_halt;;"
490 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
491 "env exists secureboot && esbc_halt;;"
494 #ifdef CONFIG_FSL_MC_ENET
495 #define CONFIG_FSL_MEMAC
496 #define RGMII_PHY1_ADDR 0x1
497 #define RGMII_PHY2_ADDR 0x2
498 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
499 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
500 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
501 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
503 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
504 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
505 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
506 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
507 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
508 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
509 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
510 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
511 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
512 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
513 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
514 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
515 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
516 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
517 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
518 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
520 #define CONFIG_ETHPRIME "DPMAC1@xgmii"
524 #define BOOT_TARGET_DEVICES(func) \
527 func(SCSI, scsi, 0) \
529 #include <config_distro_bootcmd.h>
531 #include <asm/fsl_secure_boot.h>
533 #endif /* __LS1088A_QDS_H */