include/configs/ls1088aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2020-2021 NXP
   4  */
   5
   6 #ifndef __LS1088A_QDS_H
   7 #define __LS1088A_QDS_H
   8
   9 #include "ls1088a_common.h"
  10
  11 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  12 #define SYS_NO_FLASH
  13 #endif
  14
  15 #define COUNTER_FREQUENCY_REAL          (get_board_sys_clk()/4)
  16
  17 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  18 #define SPD_EEPROM_ADDRESS              0x51
  19
  20
  21 /*
  22  * IFC Definitions
  23  */
  24 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  25 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  26 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  27 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
  28
  29 #define CONFIG_SYS_NOR0_CSPR                                    \
  30         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  31         CSPR_PORT_SIZE_16                                       | \
  32         CSPR_MSEL_NOR                                           | \
  33         CSPR_V)
  34 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  35         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  36         CSPR_PORT_SIZE_16                                       | \
  37         CSPR_MSEL_NOR                                           | \
  38         CSPR_V)
  39 #define CONFIG_SYS_NOR1_CSPR                                    \
  40         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)            | \
  41         CSPR_PORT_SIZE_16                                       | \
  42         CSPR_MSEL_NOR                                           | \
  43         CSPR_V)
  44 #define CONFIG_SYS_NOR1_CSPR_EARLY                              \
  45         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)      | \
  46         CSPR_PORT_SIZE_16                                       | \
  47         CSPR_MSEL_NOR                                           | \
  48         CSPR_V)
  49 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
  50 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
  51                                 FTIM0_NOR_TEADC(0x5) | \
  52                                 FTIM0_NOR_TAVDS(0x6) | \
  53                                 FTIM0_NOR_TEAHC(0x5))
  54 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
  55                                 FTIM1_NOR_TRAD_NOR(0x1a) | \
  56                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
  57 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x8) | \
  58                                 FTIM2_NOR_TCH(0x8) | \
  59                                 FTIM2_NOR_TWPH(0xe) | \
  60                                 FTIM2_NOR_TWP(0x1c))
  61 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  62 #define CONFIG_SYS_IFC_CCR      0x01000000
  63
  64 #ifndef SYS_NO_FLASH
  65 #define CONFIG_SYS_FLASH_QUIET_TEST
  66 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
  67
  68 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  69
  70 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
  71                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
  72 #endif
  73 #endif
  74
  75 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
  76 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
  77
  78 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  79 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  80                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  81                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
  82                                 | CSPR_V)
  83 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
  84
  85 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  86                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  87                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
  88                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
  89                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
  90                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
  91                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
  92
  93 /* ONFI NAND Flash mode0 Timing Params */
  94 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
  95                                         FTIM0_NAND_TWP(0x18)   | \
  96                                         FTIM0_NAND_TWCHT(0x07) | \
  97                                         FTIM0_NAND_TWH(0x0a))
  98 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
  99                                         FTIM1_NAND_TWBE(0x39)  | \
 100                                         FTIM1_NAND_TRR(0x0e)   | \
 101                                         FTIM1_NAND_TRP(0x18))
 102 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 103                                         FTIM2_NAND_TREH(0x0a) | \
 104                                         FTIM2_NAND_TWHRE(0x1e))
 105 #define CONFIG_SYS_NAND_FTIM3           0x0
 106
 107 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 108 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 109 #define CONFIG_MTD_NAND_VERIFY_WRITE
 110
 111 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 112 #define QIXIS_LBMAP_SWITCH              6
 113 #define QIXIS_QMAP_MASK                 0xe0
 114 #define QIXIS_QMAP_SHIFT                5
 115 #define QIXIS_LBMAP_MASK                0x0f
 116 #define QIXIS_LBMAP_SHIFT               0
 117 #define QIXIS_LBMAP_DFLTBANK            0x0e
 118 #define QIXIS_LBMAP_ALTBANK             0x2e
 119 #define QIXIS_LBMAP_SD                  0x00
 120 #define QIXIS_LBMAP_EMMC                0x00
 121 #define QIXIS_LBMAP_IFC                 0x00
 122 #define QIXIS_LBMAP_SD_QSPI             0x0e
 123 #define QIXIS_LBMAP_QSPI                0x0e
 124 #define QIXIS_RCW_SRC_IFC               0x25
 125 #define QIXIS_RCW_SRC_SD                0x40
 126 #define QIXIS_RCW_SRC_EMMC              0x41
 127 #define QIXIS_RCW_SRC_QSPI              0x62
 128 #define QIXIS_RST_CTL_RESET             0x41
 129 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 130 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 131 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 132 #define QIXIS_RST_FORCE_MEM             0x01
 133 #define QIXIS_STAT_PRES1                0xb
 134 #define QIXIS_SDID_MASK                 0x07
 135 #define QIXIS_ESDHC_NO_ADAPTER          0x7
 136
 137 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 138 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 139                                         | CSPR_PORT_SIZE_8 \
 140                                         | CSPR_MSEL_GPCM \
 141                                         | CSPR_V)
 142 #define SYS_FPGA_CSPR_FINAL     (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 143                                         | CSPR_PORT_SIZE_8 \
 144                                         | CSPR_MSEL_GPCM \
 145                                         | CSPR_V)
 146
 147 #define SYS_FPGA_AMASK          IFC_AMASK(64 * 1024)
 148 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 149 #define CONFIG_SYS_FPGA_CSOR            CSOR_GPCM_ADM_SHIFT(0)
 150 #else
 151 #define CONFIG_SYS_FPGA_CSOR            CSOR_GPCM_ADM_SHIFT(12)
 152 #endif
 153 /* QIXIS Timing parameters*/
 154 #define SYS_FPGA_CS_FTIM0       (FTIM0_GPCM_TACSE(0x0e) | \
 155                                         FTIM0_GPCM_TEADC(0x0e) | \
 156                                         FTIM0_GPCM_TEAHC(0x0e))
 157 #define SYS_FPGA_CS_FTIM1       (FTIM1_GPCM_TACO(0xff) | \
 158                                         FTIM1_GPCM_TRAD(0x3f))
 159 #define SYS_FPGA_CS_FTIM2       (FTIM2_GPCM_TCS(0xf) | \
 160                                         FTIM2_GPCM_TCH(0xf) | \
 161                                         FTIM2_GPCM_TWP(0x3E))
 162 #define SYS_FPGA_CS_FTIM3       0x0
 163
 164 #ifdef CONFIG_TFABOOT
 165 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 166 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 167 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 168 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 169 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 170 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 171 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 172 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 173 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 174 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 175 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR_EARLY
 176 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR1_CSPR
 177 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK_EARLY
 178 #define CONFIG_SYS_AMASK1_FINAL         CONFIG_SYS_NOR_AMASK
 179 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 180 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 181 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 182 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 183 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 184 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 185 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 186 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 187 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 188 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 189 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 190 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 191 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 192 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 193 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 194 #define CONFIG_SYS_CSPR3_FINAL          SYS_FPGA_CSPR_FINAL
 195 #define CONFIG_SYS_AMASK3               SYS_FPGA_AMASK
 196 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 197 #define CONFIG_SYS_CS3_FTIM0            SYS_FPGA_CS_FTIM0
 198 #define CONFIG_SYS_CS3_FTIM1            SYS_FPGA_CS_FTIM1
 199 #define CONFIG_SYS_CS3_FTIM2            SYS_FPGA_CS_FTIM2
 200 #define CONFIG_SYS_CS3_FTIM3            SYS_FPGA_CS_FTIM3
 201 #else
 202 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 203 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 204 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 205 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 206 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 207 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 208 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 209 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 210 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 211 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 212 #define CONFIG_SYS_CSPR2                CONFIG_SYS_FPGA_CSPR
 213 #define CONFIG_SYS_CSPR2_FINAL          SYS_FPGA_CSPR_FINAL
 214 #define CONFIG_SYS_AMASK2               SYS_FPGA_AMASK
 215 #define CONFIG_SYS_CSOR2                CONFIG_SYS_FPGA_CSOR
 216 #define CONFIG_SYS_CS2_FTIM0            SYS_FPGA_CS_FTIM0
 217 #define CONFIG_SYS_CS2_FTIM1            SYS_FPGA_CS_FTIM1
 218 #define CONFIG_SYS_CS2_FTIM2            SYS_FPGA_CS_FTIM2
 219 #define CONFIG_SYS_CS2_FTIM3            SYS_FPGA_CS_FTIM3
 220 #else
 221 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 222 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 223 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 224 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 225 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 226 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 227 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 228 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 229 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 230 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 231 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR_EARLY
 232 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR1_CSPR
 233 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK_EARLY
 234 #define CONFIG_SYS_AMASK1_FINAL         CONFIG_SYS_NOR_AMASK
 235 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 236 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 237 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 238 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 239 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 240 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 241 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 242 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 243 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 244 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 245 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 246 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 247 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 248 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 249 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 250 #define CONFIG_SYS_CSPR3_FINAL          SYS_FPGA_CSPR_FINAL
 251 #define CONFIG_SYS_AMASK3               SYS_FPGA_AMASK
 252 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 253 #define CONFIG_SYS_CS3_FTIM0            SYS_FPGA_CS_FTIM0
 254 #define CONFIG_SYS_CS3_FTIM1            SYS_FPGA_CS_FTIM1
 255 #define CONFIG_SYS_CS3_FTIM2            SYS_FPGA_CS_FTIM2
 256 #define CONFIG_SYS_CS3_FTIM3            SYS_FPGA_CS_FTIM3
 257 #endif
 258 #endif
 259
 260 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 261
 262 /*
 263  * I2C bus multiplexer
 264  */
 265 #define I2C_MUX_PCA_ADDR_PRI            0x77
 266 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 267 #define I2C_RETIMER_ADDR                0x18
 268 #define I2C_RETIMER_ADDR2               0x19
 269 #define I2C_MUX_CH_DEFAULT              0x8
 270 #define I2C_MUX_CH5                     0xD
 271
 272 #define I2C_MUX_CH_VOL_MONITOR          0xA
 273
 274 /* Voltage monitor on channel 2*/
 275 #define I2C_VOL_MONITOR_ADDR           0x63
 276 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 277 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 278 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 279 #define I2C_SVDD_MONITOR_ADDR           0x4F
 280
 281 /* The lowest and highest voltage allowed for LS1088AQDS */
 282 #define VDD_MV_MIN                      819
 283 #define VDD_MV_MAX                      1212
 284
 285 #define PWM_CHANNEL0                    0x0
 286
 287 /*
 288 * RTC configuration
 289 */
 290 #define RTC
 291 #define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
 292
 293 /* EEPROM */
 294 #define CONFIG_SYS_I2C_EEPROM_NXID
 295 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 296
 297 #ifdef CONFIG_FSL_DSPI
 298 #if !defined(CONFIG_TFABOOT) && \
 299         !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 300 #endif
 301 #endif
 302
 303 #define CONFIG_FSL_MEMAC
 304
 305 #define COMMON_ENV \
 306         "kernelheader_addr_r=0x80200000\0"      \
 307         "fdtheader_addr_r=0x80100000\0"         \
 308         "kernel_addr_r=0x81000000\0"            \
 309         "fdt_addr_r=0x90000000\0"               \
 310         "load_addr=0xa0000000\0"
 311
 312 /* Initial environment variables */
 313 #ifdef CONFIG_NXP_ESBC
 314 #undef CONFIG_EXTRA_ENV_SETTINGS
 315 #define CONFIG_EXTRA_ENV_SETTINGS               \
 316         COMMON_ENV                              \
 317         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 318         "loadaddr=0x90100000\0"                 \
 319         "kernel_addr=0x100000\0"                \
 320         "ramdisk_addr=0x800000\0"               \
 321         "ramdisk_size=0x2000000\0"              \
 322         "fdt_high=0xa0000000\0"                 \
 323         "initrd_high=0xffffffffffffffff\0"      \
 324         "kernel_start=0x1000000\0"              \
 325         "kernel_load=0xa0000000\0"              \
 326         "kernel_size=0x2800000\0"               \
 327         "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x200000;"  \
 328         "sf read 0xa0640000 0x640000 0x4000; esbc_validate 0xa0640000;" \
 329         "sf read 0xa0e00000 0xe00000 0x100000;" \
 330         "sf read 0xa0680000 0x680000 0x4000;esbc_validate 0xa0680000;"  \
 331         "fsl_mc start mc 0xa0a00000 0xa0e00000\0"                       \
 332         "mcmemsize=0x70000000 \0"
 333 #else /* if !(CONFIG_NXP_ESBC) */
 334 #ifdef CONFIG_TFABOOT
 335 #define QSPI_MC_INIT_CMD                                \
 336         "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"    \
 337         "sf read 0x80e00000 0xE00000 0x100000;" \
 338         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 339 #define SD_MC_INIT_CMD                          \
 340         "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
 341         "mmc read 0x80e00000 0x7000 0x800;" \
 342         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 343 #define IFC_MC_INIT_CMD                         \
 344         "fsl_mc start mc 0x580A00000 0x580E00000\0"
 345
 346 #undef CONFIG_EXTRA_ENV_SETTINGS
 347 #define CONFIG_EXTRA_ENV_SETTINGS               \
 348         COMMON_ENV                              \
 349         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 350         "loadaddr=0x90100000\0"                 \
 351         "kernel_addr=0x100000\0"                \
 352         "kernel_addr_sd=0x800\0"                \
 353         "ramdisk_addr=0x800000\0"               \
 354         "ramdisk_size=0x2000000\0"              \
 355         "fdt_high=0xa0000000\0"                 \
 356         "initrd_high=0xffffffffffffffff\0"      \
 357         "kernel_start=0x1000000\0"              \
 358         "kernel_start_sd=0x8000\0"              \
 359         "kernel_load=0xa0000000\0"              \
 360         "kernel_size=0x2800000\0"               \
 361         "kernel_size_sd=0x14000\0"               \
 362         "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"  \
 363         "sf read 0x80e00000 0xE00000 0x100000;" \
 364         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 365         "mcmemsize=0x70000000 \0"               \
 366         "BOARD=ls1088aqds\0" \
 367         "scriptaddr=0x80000000\0"               \
 368         "scripthdraddr=0x80080000\0"            \
 369         BOOTENV                                 \
 370         "boot_scripts=ls1088aqds_boot.scr\0"    \
 371         "boot_script_hdr=hdr_ls1088aqds_bs.out\0"       \
 372         "scan_dev_for_boot_part="               \
 373                 "part list ${devtype} ${devnum} devplist; "     \
 374                 "env exists devplist || setenv devplist 1; "    \
 375                 "for distro_bootpart in ${devplist}; do "       \
 376                         "if fstype ${devtype} "                 \
 377                                 "${devnum}:${distro_bootpart} " \
 378                                 "bootfstype; then "             \
 379                                 "run scan_dev_for_boot; "       \
 380                         "fi; "                                  \
 381                 "done\0"                                        \
 382         "boot_a_script="                                        \
 383                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 384                 "${scriptaddr} ${prefix}${script}; "            \
 385         "env exists secureboot && load ${devtype} "             \
 386                 "${devnum}:${distro_bootpart} "                 \
 387                 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
 388                 "env exists secureboot "                        \
 389                 "&& esbc_validate ${scripthdraddr};"            \
 390                 "source ${scriptaddr}\0"                        \
 391         "qspi_bootcmd=echo Trying load from qspi..; " \
 392                 "sf probe 0:0; " \
 393                 "sf read 0x80001000 0xd00000 0x100000; " \
 394                 "fsl_mc lazyapply dpl 0x80001000 && " \
 395                 "sf read $kernel_load $kernel_start " \
 396                 "$kernel_size && bootm $kernel_load#$BOARD\0" \
 397         "sd_bootcmd=echo Trying load from sd card..; " \
 398                 "mmcinfo;mmc read 0x80001000 0x6800 0x800; "\
 399                 "fsl_mc lazyapply dpl 0x80001000 && " \
 400                 "mmc read $kernel_load $kernel_start_sd " \
 401                 "$kernel_size_sd && bootm $kernel_load#$BOARD\0" \
 402         "nor_bootcmd=echo Trying load from nor..; " \
 403                 "fsl_mc lazyapply dpl 0x580d00000 && " \
 404                 "cp.b $kernel_start $kernel_load " \
 405                 "$kernel_size && bootm $kernel_load#$BOARD\0"
 406 #else
 407 #if defined(CONFIG_QSPI_BOOT)
 408 #undef CONFIG_EXTRA_ENV_SETTINGS
 409 #define CONFIG_EXTRA_ENV_SETTINGS               \
 410         COMMON_ENV                              \
 411         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 412         "loadaddr=0x90100000\0"                 \
 413         "kernel_addr=0x100000\0"                \
 414         "ramdisk_addr=0x800000\0"               \
 415         "ramdisk_size=0x2000000\0"              \
 416         "fdt_high=0xa0000000\0"                 \
 417         "initrd_high=0xffffffffffffffff\0"      \
 418         "kernel_start=0x1000000\0"              \
 419         "kernel_load=0xa0000000\0"              \
 420         "kernel_size=0x2800000\0"               \
 421         "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"  \
 422         "sf read 0x80e00000 0xE00000 0x100000;" \
 423         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 424         "mcmemsize=0x70000000 \0"
 425 #elif defined(CONFIG_SD_BOOT)
 426 #undef CONFIG_EXTRA_ENV_SETTINGS
 427 #define CONFIG_EXTRA_ENV_SETTINGS               \
 428         COMMON_ENV                              \
 429         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 430         "loadaddr=0x90100000\0"                 \
 431         "kernel_addr=0x800\0"                \
 432         "ramdisk_addr=0x800000\0"               \
 433         "ramdisk_size=0x2000000\0"              \
 434         "fdt_high=0xa0000000\0"                 \
 435         "initrd_high=0xffffffffffffffff\0"      \
 436         "kernel_start=0x8000\0"              \
 437         "kernel_load=0xa0000000\0"              \
 438         "kernel_size=0x14000\0"               \
 439         "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
 440         "mmc read 0x80e00000 0x7000 0x800;" \
 441         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 442         "mcmemsize=0x70000000 \0"
 443 #else   /* NOR BOOT */
 444 #undef CONFIG_EXTRA_ENV_SETTINGS
 445 #define CONFIG_EXTRA_ENV_SETTINGS               \
 446         COMMON_ENV                              \
 447         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 448         "loadaddr=0x90100000\0"                 \
 449         "kernel_addr=0x100000\0"                \
 450         "ramdisk_addr=0x800000\0"               \
 451         "ramdisk_size=0x2000000\0"              \
 452         "fdt_high=0xa0000000\0"                 \
 453         "initrd_high=0xffffffffffffffff\0"      \
 454         "kernel_start=0x1000000\0"              \
 455         "kernel_load=0xa0000000\0"              \
 456         "kernel_size=0x2800000\0"               \
 457         "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0"   \
 458         "mcmemsize=0x70000000 \0"
 459 #endif
 460 #endif /* CONFIG_TFABOOT */
 461 #endif /* CONFIG_NXP_ESBC */
 462
 463 #ifdef CONFIG_TFABOOT
 464 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "   \
 465                            "env exists secureboot && esbc_halt;;"
 466 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "     \
 467                            "env exists secureboot && esbc_halt;;"
 468 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "   \
 469                            "env exists secureboot && esbc_halt;;"
 470 #endif
 471
 472 #ifdef CONFIG_FSL_MC_ENET
 473 #define CONFIG_FSL_MEMAC
 474 #define RGMII_PHY1_ADDR         0x1
 475 #define RGMII_PHY2_ADDR         0x2
 476 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 477 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
 478 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 479 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 480
 481 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
 482 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
 483 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
 484 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
 485 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
 486 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
 487 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
 488 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
 489 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
 490 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
 491 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
 492 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
 493 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
 494 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
 495 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
 496 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
 497
 498 #endif
 499
 500 #define BOOT_TARGET_DEVICES(func) \
 501         func(USB, usb, 0) \
 502         func(MMC, mmc, 0) \
 503         func(SCSI, scsi, 0) \
 504         func(DHCP, dhcp, na)
 505 #include <config_distro_bootcmd.h>
 506
 507 #include <asm/fsl_secure_boot.h>
 508
 509 #endif /* __LS1088A_QDS_H */