include/configs/ls1088aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2020-2021 NXP
   4  */
   5
   6 #ifndef __LS1088A_QDS_H
   7 #define __LS1088A_QDS_H
   8
   9 #include "ls1088a_common.h"
  10
  11 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  12 #define SYS_NO_FLASH
  13 #endif
  14
  15 #define COUNTER_FREQUENCY_REAL          (get_board_sys_clk()/4)
  16
  17 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  18 #define SPD_EEPROM_ADDRESS              0x51
  19
  20
  21 /*
  22  * IFC Definitions
  23  */
  24 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  25 #define CFG_SYS_NOR0_CSPR_EXT   (0x0)
  26 #define CFG_SYS_NOR_AMASK               IFC_AMASK(128*1024*1024)
  27 #define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
  28
  29 #define CFG_SYS_NOR0_CSPR                                       \
  30         (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS)                | \
  31         CSPR_PORT_SIZE_16                                       | \
  32         CSPR_MSEL_NOR                                           | \
  33         CSPR_V)
  34 #define CFG_SYS_NOR0_CSPR_EARLY                         \
  35         (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY)  | \
  36         CSPR_PORT_SIZE_16                                       | \
  37         CSPR_MSEL_NOR                                           | \
  38         CSPR_V)
  39 #define CFG_SYS_NOR1_CSPR                                       \
  40         (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS)               | \
  41         CSPR_PORT_SIZE_16                                       | \
  42         CSPR_MSEL_NOR                                           | \
  43         CSPR_V)
  44 #define CFG_SYS_NOR1_CSPR_EARLY                         \
  45         (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS_EARLY) | \
  46         CSPR_PORT_SIZE_16                                       | \
  47         CSPR_MSEL_NOR                                           | \
  48         CSPR_V)
  49 #define CFG_SYS_NOR_CSOR        CSOR_NOR_ADM_SHIFT(12)
  50 #define CFG_SYS_NOR_FTIM0       (FTIM0_NOR_TACSE(0x4) | \
  51                                 FTIM0_NOR_TEADC(0x5) | \
  52                                 FTIM0_NOR_TAVDS(0x6) | \
  53                                 FTIM0_NOR_TEAHC(0x5))
  54 #define CFG_SYS_NOR_FTIM1       (FTIM1_NOR_TACO(0x35) | \
  55                                 FTIM1_NOR_TRAD_NOR(0x1a) | \
  56                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
  57 #define CFG_SYS_NOR_FTIM2       (FTIM2_NOR_TCS(0x8) | \
  58                                 FTIM2_NOR_TCH(0x8) | \
  59                                 FTIM2_NOR_TWPH(0xe) | \
  60                                 FTIM2_NOR_TWP(0x1c))
  61 #define CFG_SYS_NOR_FTIM3       0x04000000
  62 #define CFG_SYS_IFC_CCR 0x01000000
  63
  64 #ifndef SYS_NO_FLASH
  65 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
  66
  67 #define CFG_SYS_FLASH_BANKS_LIST        { CFG_SYS_FLASH_BASE,\
  68                                          CFG_SYS_FLASH_BASE + 0x40000000}
  69 #endif
  70 #endif
  71
  72 #define CFG_SYS_NAND_CSPR_EXT   (0x0)
  73 #define CFG_SYS_NAND_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
  74                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  75                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
  76                                 | CSPR_V)
  77 #define CFG_SYS_NAND_AMASK      IFC_AMASK(64 * 1024)
  78
  79 #define CFG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  80                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  81                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
  82                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
  83                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
  84                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
  85                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
  86
  87 /* ONFI NAND Flash mode0 Timing Params */
  88 #define CFG_SYS_NAND_FTIM0              (FTIM0_NAND_TCCST(0x07) | \
  89                                         FTIM0_NAND_TWP(0x18)   | \
  90                                         FTIM0_NAND_TWCHT(0x07) | \
  91                                         FTIM0_NAND_TWH(0x0a))
  92 #define CFG_SYS_NAND_FTIM1              (FTIM1_NAND_TADLE(0x32) | \
  93                                         FTIM1_NAND_TWBE(0x39)  | \
  94                                         FTIM1_NAND_TRR(0x0e)   | \
  95                                         FTIM1_NAND_TRP(0x18))
  96 #define CFG_SYS_NAND_FTIM2              (FTIM2_NAND_TRAD(0x0f) | \
  97                                         FTIM2_NAND_TREH(0x0a) | \
  98                                         FTIM2_NAND_TWHRE(0x1e))
  99 #define CFG_SYS_NAND_FTIM3              0x0
 100
 101 #define CFG_SYS_NAND_BASE_LIST  { CFG_SYS_NAND_BASE }
 102 #define CONFIG_MTD_NAND_VERIFY_WRITE
 103
 104 #define CFG_SYS_I2C_FPGA_ADDR   0x66
 105 #define QIXIS_LBMAP_SWITCH              6
 106 #define QIXIS_QMAP_MASK                 0xe0
 107 #define QIXIS_QMAP_SHIFT                5
 108 #define QIXIS_LBMAP_MASK                0x0f
 109 #define QIXIS_LBMAP_SHIFT               0
 110 #define QIXIS_LBMAP_DFLTBANK            0x0e
 111 #define QIXIS_LBMAP_ALTBANK             0x2e
 112 #define QIXIS_LBMAP_SD                  0x00
 113 #define QIXIS_LBMAP_EMMC                0x00
 114 #define QIXIS_LBMAP_IFC                 0x00
 115 #define QIXIS_LBMAP_SD_QSPI             0x0e
 116 #define QIXIS_LBMAP_QSPI                0x0e
 117 #define QIXIS_RCW_SRC_IFC               0x25
 118 #define QIXIS_RCW_SRC_SD                0x40
 119 #define QIXIS_RCW_SRC_EMMC              0x41
 120 #define QIXIS_RCW_SRC_QSPI              0x62
 121 #define QIXIS_RST_CTL_RESET             0x41
 122 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 123 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 124 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 125 #define QIXIS_RST_FORCE_MEM             0x01
 126 #define QIXIS_STAT_PRES1                0xb
 127 #define QIXIS_SDID_MASK                 0x07
 128 #define QIXIS_ESDHC_NO_ADAPTER          0x7
 129
 130 #define CFG_SYS_FPGA_CSPR_EXT   (0x0)
 131 #define CFG_SYS_FPGA_CSPR               (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 132                                         | CSPR_PORT_SIZE_8 \
 133                                         | CSPR_MSEL_GPCM \
 134                                         | CSPR_V)
 135 #define SYS_FPGA_CSPR_FINAL     (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 136                                         | CSPR_PORT_SIZE_8 \
 137                                         | CSPR_MSEL_GPCM \
 138                                         | CSPR_V)
 139
 140 #define SYS_FPGA_AMASK          IFC_AMASK(64 * 1024)
 141 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 142 #define CFG_SYS_FPGA_CSOR               CSOR_GPCM_ADM_SHIFT(0)
 143 #else
 144 #define CFG_SYS_FPGA_CSOR               CSOR_GPCM_ADM_SHIFT(12)
 145 #endif
 146 /* QIXIS Timing parameters*/
 147 #define SYS_FPGA_CS_FTIM0       (FTIM0_GPCM_TACSE(0x0e) | \
 148                                         FTIM0_GPCM_TEADC(0x0e) | \
 149                                         FTIM0_GPCM_TEAHC(0x0e))
 150 #define SYS_FPGA_CS_FTIM1       (FTIM1_GPCM_TACO(0xff) | \
 151                                         FTIM1_GPCM_TRAD(0x3f))
 152 #define SYS_FPGA_CS_FTIM2       (FTIM2_GPCM_TCS(0xf) | \
 153                                         FTIM2_GPCM_TCH(0xf) | \
 154                                         FTIM2_GPCM_TWP(0x3E))
 155 #define SYS_FPGA_CS_FTIM3       0x0
 156
 157 #ifdef CONFIG_TFABOOT
 158 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NOR0_CSPR_EXT
 159 #define CFG_SYS_CSPR0           CFG_SYS_NOR0_CSPR_EARLY
 160 #define CFG_SYS_CSPR0_FINAL             CFG_SYS_NOR0_CSPR
 161 #define CFG_SYS_AMASK0          CFG_SYS_NOR_AMASK
 162 #define CFG_SYS_CSOR0           CFG_SYS_NOR_CSOR
 163 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NOR_FTIM0
 164 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NOR_FTIM1
 165 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NOR_FTIM2
 166 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NOR_FTIM3
 167 #define CFG_SYS_CSPR1_EXT               CFG_SYS_NOR0_CSPR_EXT
 168 #define CFG_SYS_CSPR1           CFG_SYS_NOR1_CSPR_EARLY
 169 #define CFG_SYS_CSPR1_FINAL             CFG_SYS_NOR1_CSPR
 170 #define CFG_SYS_AMASK1          CFG_SYS_NOR_AMASK_EARLY
 171 #define CFG_SYS_AMASK1_FINAL            CFG_SYS_NOR_AMASK
 172 #define CFG_SYS_CSOR1           CFG_SYS_NOR_CSOR
 173 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NOR_FTIM0
 174 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NOR_FTIM1
 175 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NOR_FTIM2
 176 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NOR_FTIM3
 177 #define CFG_SYS_CSPR2_EXT               CFG_SYS_NAND_CSPR_EXT
 178 #define CFG_SYS_CSPR2           CFG_SYS_NAND_CSPR
 179 #define CFG_SYS_AMASK2          CFG_SYS_NAND_AMASK
 180 #define CFG_SYS_CSOR2           CFG_SYS_NAND_CSOR
 181 #define CFG_SYS_CS2_FTIM0               CFG_SYS_NAND_FTIM0
 182 #define CFG_SYS_CS2_FTIM1               CFG_SYS_NAND_FTIM1
 183 #define CFG_SYS_CS2_FTIM2               CFG_SYS_NAND_FTIM2
 184 #define CFG_SYS_CS2_FTIM3               CFG_SYS_NAND_FTIM3
 185 #define CFG_SYS_CSPR3_EXT               CFG_SYS_FPGA_CSPR_EXT
 186 #define CFG_SYS_CSPR3           CFG_SYS_FPGA_CSPR
 187 #define CFG_SYS_CSPR3_FINAL             SYS_FPGA_CSPR_FINAL
 188 #define CFG_SYS_AMASK3          SYS_FPGA_AMASK
 189 #define CFG_SYS_CSOR3           CFG_SYS_FPGA_CSOR
 190 #define CFG_SYS_CS3_FTIM0               SYS_FPGA_CS_FTIM0
 191 #define CFG_SYS_CS3_FTIM1               SYS_FPGA_CS_FTIM1
 192 #define CFG_SYS_CS3_FTIM2               SYS_FPGA_CS_FTIM2
 193 #define CFG_SYS_CS3_FTIM3               SYS_FPGA_CS_FTIM3
 194 #else
 195 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 196 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NAND_CSPR_EXT
 197 #define CFG_SYS_CSPR0           CFG_SYS_NAND_CSPR
 198 #define CFG_SYS_AMASK0          CFG_SYS_NAND_AMASK
 199 #define CFG_SYS_CSOR0           CFG_SYS_NAND_CSOR
 200 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NAND_FTIM0
 201 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NAND_FTIM1
 202 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NAND_FTIM2
 203 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NAND_FTIM3
 204 #define CFG_SYS_CSPR2_EXT               CFG_SYS_FPGA_CSPR_EXT
 205 #define CFG_SYS_CSPR2           CFG_SYS_FPGA_CSPR
 206 #define CFG_SYS_CSPR2_FINAL             SYS_FPGA_CSPR_FINAL
 207 #define CFG_SYS_AMASK2          SYS_FPGA_AMASK
 208 #define CFG_SYS_CSOR2           CFG_SYS_FPGA_CSOR
 209 #define CFG_SYS_CS2_FTIM0               SYS_FPGA_CS_FTIM0
 210 #define CFG_SYS_CS2_FTIM1               SYS_FPGA_CS_FTIM1
 211 #define CFG_SYS_CS2_FTIM2               SYS_FPGA_CS_FTIM2
 212 #define CFG_SYS_CS2_FTIM3               SYS_FPGA_CS_FTIM3
 213 #else
 214 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NOR0_CSPR_EXT
 215 #define CFG_SYS_CSPR0           CFG_SYS_NOR0_CSPR_EARLY
 216 #define CFG_SYS_CSPR0_FINAL             CFG_SYS_NOR0_CSPR
 217 #define CFG_SYS_AMASK0          CFG_SYS_NOR_AMASK
 218 #define CFG_SYS_CSOR0           CFG_SYS_NOR_CSOR
 219 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NOR_FTIM0
 220 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NOR_FTIM1
 221 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NOR_FTIM2
 222 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NOR_FTIM3
 223 #define CFG_SYS_CSPR1_EXT               CFG_SYS_NOR0_CSPR_EXT
 224 #define CFG_SYS_CSPR1           CFG_SYS_NOR1_CSPR_EARLY
 225 #define CFG_SYS_CSPR1_FINAL             CFG_SYS_NOR1_CSPR
 226 #define CFG_SYS_AMASK1          CFG_SYS_NOR_AMASK_EARLY
 227 #define CFG_SYS_AMASK1_FINAL            CFG_SYS_NOR_AMASK
 228 #define CFG_SYS_CSOR1           CFG_SYS_NOR_CSOR
 229 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NOR_FTIM0
 230 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NOR_FTIM1
 231 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NOR_FTIM2
 232 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NOR_FTIM3
 233 #define CFG_SYS_CSPR2_EXT               CFG_SYS_NAND_CSPR_EXT
 234 #define CFG_SYS_CSPR2           CFG_SYS_NAND_CSPR
 235 #define CFG_SYS_AMASK2          CFG_SYS_NAND_AMASK
 236 #define CFG_SYS_CSOR2           CFG_SYS_NAND_CSOR
 237 #define CFG_SYS_CS2_FTIM0               CFG_SYS_NAND_FTIM0
 238 #define CFG_SYS_CS2_FTIM1               CFG_SYS_NAND_FTIM1
 239 #define CFG_SYS_CS2_FTIM2               CFG_SYS_NAND_FTIM2
 240 #define CFG_SYS_CS2_FTIM3               CFG_SYS_NAND_FTIM3
 241 #define CFG_SYS_CSPR3_EXT               CFG_SYS_FPGA_CSPR_EXT
 242 #define CFG_SYS_CSPR3           CFG_SYS_FPGA_CSPR
 243 #define CFG_SYS_CSPR3_FINAL             SYS_FPGA_CSPR_FINAL
 244 #define CFG_SYS_AMASK3          SYS_FPGA_AMASK
 245 #define CFG_SYS_CSOR3           CFG_SYS_FPGA_CSOR
 246 #define CFG_SYS_CS3_FTIM0               SYS_FPGA_CS_FTIM0
 247 #define CFG_SYS_CS3_FTIM1               SYS_FPGA_CS_FTIM1
 248 #define CFG_SYS_CS3_FTIM2               SYS_FPGA_CS_FTIM2
 249 #define CFG_SYS_CS3_FTIM3               SYS_FPGA_CS_FTIM3
 250 #endif
 251 #endif
 252
 253 #define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 254
 255 /*
 256  * I2C bus multiplexer
 257  */
 258 #define I2C_MUX_PCA_ADDR_PRI            0x77
 259 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 260 #define I2C_RETIMER_ADDR                0x18
 261 #define I2C_RETIMER_ADDR2               0x19
 262 #define I2C_MUX_CH_DEFAULT              0x8
 263 #define I2C_MUX_CH5                     0xD
 264
 265 #define I2C_MUX_CH_VOL_MONITOR          0xA
 266
 267 /* Voltage monitor on channel 2*/
 268 #define I2C_VOL_MONITOR_ADDR           0x63
 269 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 270 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 271 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 272 #define I2C_SVDD_MONITOR_ADDR           0x4F
 273
 274 /* The lowest and highest voltage allowed for LS1088AQDS */
 275 #define VDD_MV_MIN                      819
 276 #define VDD_MV_MAX                      1212
 277
 278 #define PWM_CHANNEL0                    0x0
 279
 280 /*
 281 * RTC configuration
 282 */
 283 #define CFG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
 284
 285 #ifdef CONFIG_FSL_DSPI
 286 #if !defined(CONFIG_TFABOOT) && \
 287         !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 288 #endif
 289 #endif
 290
 291 #define COMMON_ENV \
 292         "kernelheader_addr_r=0x80200000\0"      \
 293         "fdtheader_addr_r=0x80100000\0"         \
 294         "kernel_addr_r=0x81000000\0"            \
 295         "fdt_addr_r=0x90000000\0"               \
 296         "load_addr=0xa0000000\0"
 297
 298 /* Initial environment variables */
 299 #ifdef CONFIG_NXP_ESBC
 300 #undef CONFIG_EXTRA_ENV_SETTINGS
 301 #define CONFIG_EXTRA_ENV_SETTINGS               \
 302         COMMON_ENV                              \
 303         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 304         "loadaddr=0x90100000\0"                 \
 305         "kernel_addr=0x100000\0"                \
 306         "ramdisk_addr=0x800000\0"               \
 307         "ramdisk_size=0x2000000\0"              \
 308         "fdt_high=0xa0000000\0"                 \
 309         "initrd_high=0xffffffffffffffff\0"      \
 310         "kernel_start=0x1000000\0"              \
 311         "kernel_load=0xa0000000\0"              \
 312         "kernel_size=0x2800000\0"               \
 313         "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x200000;"  \
 314         "sf read 0xa0640000 0x640000 0x4000; esbc_validate 0xa0640000;" \
 315         "sf read 0xa0e00000 0xe00000 0x100000;" \
 316         "sf read 0xa0680000 0x680000 0x4000;esbc_validate 0xa0680000;"  \
 317         "fsl_mc start mc 0xa0a00000 0xa0e00000\0"                       \
 318         "mcmemsize=0x70000000 \0"
 319 #else /* if !(CONFIG_NXP_ESBC) */
 320 #ifdef CONFIG_TFABOOT
 321 #define QSPI_MC_INIT_CMD                                \
 322         "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"    \
 323         "sf read 0x80e00000 0xE00000 0x100000;" \
 324         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 325 #define SD_MC_INIT_CMD                          \
 326         "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
 327         "mmc read 0x80e00000 0x7000 0x800;" \
 328         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 329 #define IFC_MC_INIT_CMD                         \
 330         "fsl_mc start mc 0x580A00000 0x580E00000\0"
 331
 332 #undef CONFIG_EXTRA_ENV_SETTINGS
 333 #define CONFIG_EXTRA_ENV_SETTINGS               \
 334         COMMON_ENV                              \
 335         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 336         "loadaddr=0x90100000\0"                 \
 337         "kernel_addr=0x100000\0"                \
 338         "kernel_addr_sd=0x800\0"                \
 339         "ramdisk_addr=0x800000\0"               \
 340         "ramdisk_size=0x2000000\0"              \
 341         "fdt_high=0xa0000000\0"                 \
 342         "initrd_high=0xffffffffffffffff\0"      \
 343         "kernel_start=0x1000000\0"              \
 344         "kernel_start_sd=0x8000\0"              \
 345         "kernel_load=0xa0000000\0"              \
 346         "kernel_size=0x2800000\0"               \
 347         "kernel_size_sd=0x14000\0"               \
 348         "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"  \
 349         "sf read 0x80e00000 0xE00000 0x100000;" \
 350         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 351         "mcmemsize=0x70000000 \0"               \
 352         "BOARD=ls1088aqds\0" \
 353         "scriptaddr=0x80000000\0"               \
 354         "scripthdraddr=0x80080000\0"            \
 355         BOOTENV                                 \
 356         "boot_scripts=ls1088aqds_boot.scr\0"    \
 357         "boot_script_hdr=hdr_ls1088aqds_bs.out\0"       \
 358         "scan_dev_for_boot_part="               \
 359                 "part list ${devtype} ${devnum} devplist; "     \
 360                 "env exists devplist || setenv devplist 1; "    \
 361                 "for distro_bootpart in ${devplist}; do "       \
 362                         "if fstype ${devtype} "                 \
 363                                 "${devnum}:${distro_bootpart} " \
 364                                 "bootfstype; then "             \
 365                                 "run scan_dev_for_boot; "       \
 366                         "fi; "                                  \
 367                 "done\0"                                        \
 368         "boot_a_script="                                        \
 369                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 370                 "${scriptaddr} ${prefix}${script}; "            \
 371         "env exists secureboot && load ${devtype} "             \
 372                 "${devnum}:${distro_bootpart} "                 \
 373                 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
 374                 "env exists secureboot "                        \
 375                 "&& esbc_validate ${scripthdraddr};"            \
 376                 "source ${scriptaddr}\0"                        \
 377         "qspi_bootcmd=echo Trying load from qspi..; " \
 378                 "sf probe 0:0; " \
 379                 "sf read 0x80001000 0xd00000 0x100000; " \
 380                 "fsl_mc lazyapply dpl 0x80001000 && " \
 381                 "sf read $kernel_load $kernel_start " \
 382                 "$kernel_size && bootm $kernel_load#$BOARD\0" \
 383         "sd_bootcmd=echo Trying load from sd card..; " \
 384                 "mmcinfo;mmc read 0x80001000 0x6800 0x800; "\
 385                 "fsl_mc lazyapply dpl 0x80001000 && " \
 386                 "mmc read $kernel_load $kernel_start_sd " \
 387                 "$kernel_size_sd && bootm $kernel_load#$BOARD\0" \
 388         "nor_bootcmd=echo Trying load from nor..; " \
 389                 "fsl_mc lazyapply dpl 0x580d00000 && " \
 390                 "cp.b $kernel_start $kernel_load " \
 391                 "$kernel_size && bootm $kernel_load#$BOARD\0"
 392 #else
 393 #if defined(CONFIG_QSPI_BOOT)
 394 #undef CONFIG_EXTRA_ENV_SETTINGS
 395 #define CONFIG_EXTRA_ENV_SETTINGS               \
 396         COMMON_ENV                              \
 397         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 398         "loadaddr=0x90100000\0"                 \
 399         "kernel_addr=0x100000\0"                \
 400         "ramdisk_addr=0x800000\0"               \
 401         "ramdisk_size=0x2000000\0"              \
 402         "fdt_high=0xa0000000\0"                 \
 403         "initrd_high=0xffffffffffffffff\0"      \
 404         "kernel_start=0x1000000\0"              \
 405         "kernel_load=0xa0000000\0"              \
 406         "kernel_size=0x2800000\0"               \
 407         "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"  \
 408         "sf read 0x80e00000 0xE00000 0x100000;" \
 409         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 410         "mcmemsize=0x70000000 \0"
 411 #elif defined(CONFIG_SD_BOOT)
 412 #undef CONFIG_EXTRA_ENV_SETTINGS
 413 #define CONFIG_EXTRA_ENV_SETTINGS               \
 414         COMMON_ENV                              \
 415         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 416         "loadaddr=0x90100000\0"                 \
 417         "kernel_addr=0x800\0"                \
 418         "ramdisk_addr=0x800000\0"               \
 419         "ramdisk_size=0x2000000\0"              \
 420         "fdt_high=0xa0000000\0"                 \
 421         "initrd_high=0xffffffffffffffff\0"      \
 422         "kernel_start=0x8000\0"              \
 423         "kernel_load=0xa0000000\0"              \
 424         "kernel_size=0x14000\0"               \
 425         "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
 426         "mmc read 0x80e00000 0x7000 0x800;" \
 427         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 428         "mcmemsize=0x70000000 \0"
 429 #else   /* NOR BOOT */
 430 #undef CONFIG_EXTRA_ENV_SETTINGS
 431 #define CONFIG_EXTRA_ENV_SETTINGS               \
 432         COMMON_ENV                              \
 433         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 434         "loadaddr=0x90100000\0"                 \
 435         "kernel_addr=0x100000\0"                \
 436         "ramdisk_addr=0x800000\0"               \
 437         "ramdisk_size=0x2000000\0"              \
 438         "fdt_high=0xa0000000\0"                 \
 439         "initrd_high=0xffffffffffffffff\0"      \
 440         "kernel_start=0x1000000\0"              \
 441         "kernel_load=0xa0000000\0"              \
 442         "kernel_size=0x2800000\0"               \
 443         "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0"   \
 444         "mcmemsize=0x70000000 \0"
 445 #endif
 446 #endif /* CONFIG_TFABOOT */
 447 #endif /* CONFIG_NXP_ESBC */
 448
 449 #ifdef CONFIG_TFABOOT
 450 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "   \
 451                            "env exists secureboot && esbc_halt;;"
 452 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "     \
 453                            "env exists secureboot && esbc_halt;;"
 454 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "   \
 455                            "env exists secureboot && esbc_halt;;"
 456 #endif
 457
 458 #ifdef CONFIG_FSL_MC_ENET
 459 #define RGMII_PHY1_ADDR         0x1
 460 #define RGMII_PHY2_ADDR         0x2
 461 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 462 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
 463 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 464 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 465
 466 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
 467 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
 468 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
 469 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
 470 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
 471 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
 472 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
 473 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
 474 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
 475 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
 476 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
 477 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
 478 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
 479 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
 480 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
 481 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
 482
 483 #endif
 484
 485 #define BOOT_TARGET_DEVICES(func) \
 486         func(USB, usb, 0) \
 487         func(MMC, mmc, 0) \
 488         func(SCSI, scsi, 0) \
 489         func(DHCP, dhcp, na)
 490 #include <config_distro_bootcmd.h>
 491
 492 #include <asm/fsl_secure_boot.h>
 493
 494 #endif /* __LS1088A_QDS_H */