1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2020-2021 NXP
6 #ifndef __LS1088A_QDS_H
7 #define __LS1088A_QDS_H
9 #include "ls1088a_common.h"
11 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
12 #define CONFIG_QIXIS_I2C_ACCESS
15 #define CONFIG_QIXIS_I2C_ACCESS
18 #define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
19 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
21 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
23 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
24 #define SPD_EEPROM_ADDRESS 0x51
25 #define CONFIG_SYS_SPD_BUS_NUM 0
31 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
32 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
33 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
34 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
36 #define CONFIG_SYS_NOR0_CSPR \
37 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
41 #define CONFIG_SYS_NOR0_CSPR_EARLY \
42 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
46 #define CONFIG_SYS_NOR1_CSPR \
47 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
51 #define CONFIG_SYS_NOR1_CSPR_EARLY \
52 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
56 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
57 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
58 FTIM0_NOR_TEADC(0x5) | \
59 FTIM0_NOR_TAVDS(0x6) | \
61 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
62 FTIM1_NOR_TRAD_NOR(0x1a) | \
63 FTIM1_NOR_TSEQRAD_NOR(0x13))
64 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \
65 FTIM2_NOR_TCH(0x8) | \
66 FTIM2_NOR_TWPH(0xe) | \
68 #define CONFIG_SYS_NOR_FTIM3 0x04000000
69 #define CONFIG_SYS_IFC_CCR 0x01000000
72 #define CONFIG_SYS_FLASH_QUIET_TEST
73 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
75 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
76 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
77 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
79 #define CONFIG_SYS_FLASH_EMPTY_INFO
80 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
81 CONFIG_SYS_FLASH_BASE + 0x40000000}
85 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
86 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
88 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
89 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
90 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
91 | CSPR_MSEL_NAND /* MSEL = NAND */ \
93 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
95 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
96 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
97 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
98 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
99 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
100 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
101 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
103 /* ONFI NAND Flash mode0 Timing Params */
104 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
105 FTIM0_NAND_TWP(0x18) | \
106 FTIM0_NAND_TWCHT(0x07) | \
107 FTIM0_NAND_TWH(0x0a))
108 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
109 FTIM1_NAND_TWBE(0x39) | \
110 FTIM1_NAND_TRR(0x0e) | \
111 FTIM1_NAND_TRP(0x18))
112 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
113 FTIM2_NAND_TREH(0x0a) | \
114 FTIM2_NAND_TWHRE(0x1e))
115 #define CONFIG_SYS_NAND_FTIM3 0x0
117 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
118 #define CONFIG_SYS_MAX_NAND_DEVICE 1
119 #define CONFIG_MTD_NAND_VERIFY_WRITE
121 #define CONFIG_FSL_QIXIS
122 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
123 #define QIXIS_LBMAP_SWITCH 6
124 #define QIXIS_QMAP_MASK 0xe0
125 #define QIXIS_QMAP_SHIFT 5
126 #define QIXIS_LBMAP_MASK 0x0f
127 #define QIXIS_LBMAP_SHIFT 0
128 #define QIXIS_LBMAP_DFLTBANK 0x0e
129 #define QIXIS_LBMAP_ALTBANK 0x2e
130 #define QIXIS_LBMAP_SD 0x00
131 #define QIXIS_LBMAP_EMMC 0x00
132 #define QIXIS_LBMAP_IFC 0x00
133 #define QIXIS_LBMAP_SD_QSPI 0x0e
134 #define QIXIS_LBMAP_QSPI 0x0e
135 #define QIXIS_RCW_SRC_IFC 0x25
136 #define QIXIS_RCW_SRC_SD 0x40
137 #define QIXIS_RCW_SRC_EMMC 0x41
138 #define QIXIS_RCW_SRC_QSPI 0x62
139 #define QIXIS_RST_CTL_RESET 0x41
140 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
141 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
142 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
143 #define QIXIS_RST_FORCE_MEM 0x01
144 #define QIXIS_STAT_PRES1 0xb
145 #define QIXIS_SDID_MASK 0x07
146 #define QIXIS_ESDHC_NO_ADAPTER 0x7
148 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
149 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
153 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
158 #define SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
159 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
160 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
162 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12)
164 /* QIXIS Timing parameters*/
165 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
166 FTIM0_GPCM_TEADC(0x0e) | \
167 FTIM0_GPCM_TEAHC(0x0e))
168 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
169 FTIM1_GPCM_TRAD(0x3f))
170 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
171 FTIM2_GPCM_TCH(0xf) | \
172 FTIM2_GPCM_TWP(0x3E))
173 #define SYS_FPGA_CS_FTIM3 0x0
175 #ifdef CONFIG_TFABOOT
176 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
177 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
178 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
179 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
180 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
181 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
182 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
183 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
184 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
185 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
186 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
187 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
188 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
189 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
190 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
191 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
192 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
193 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
194 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
195 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
196 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
197 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
198 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
199 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
200 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
201 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
202 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
203 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
204 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
205 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
206 #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
207 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
208 #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
209 #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
210 #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
211 #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
213 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
214 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
215 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
216 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
217 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
218 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
219 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
220 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
221 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
222 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
223 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
224 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
225 #define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK
226 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
227 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
228 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
229 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
230 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
232 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
233 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
234 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
235 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
236 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
237 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
238 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
239 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
240 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
241 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
242 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
243 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
244 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
245 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
246 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
247 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
248 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
249 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
250 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
251 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
252 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
253 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
254 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
255 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
256 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
257 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
258 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
259 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
260 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
261 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
262 #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
263 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
264 #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
265 #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
266 #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
267 #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
271 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
274 * I2C bus multiplexer
276 #define I2C_MUX_PCA_ADDR_PRI 0x77
277 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
278 #define I2C_RETIMER_ADDR 0x18
279 #define I2C_RETIMER_ADDR2 0x19
280 #define I2C_MUX_CH_DEFAULT 0x8
281 #define I2C_MUX_CH5 0xD
283 #define I2C_MUX_CH_VOL_MONITOR 0xA
285 /* Voltage monitor on channel 2*/
286 #define I2C_VOL_MONITOR_ADDR 0x63
287 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
288 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
289 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
290 #define I2C_SVDD_MONITOR_ADDR 0x4F
292 /* The lowest and highest voltage allowed for LS1088AQDS */
293 #define VDD_MV_MIN 819
294 #define VDD_MV_MAX 1212
296 #define PWM_CHANNEL0 0x0
302 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
305 #define CONFIG_SYS_I2C_EEPROM_NXID
306 #define CONFIG_SYS_EEPROM_BUS_NUM 0
308 #ifdef CONFIG_FSL_DSPI
309 #if !defined(CONFIG_TFABOOT) && \
310 !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
314 #define CONFIG_FSL_MEMAC
317 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
318 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
321 "kernelheader_addr_r=0x80200000\0" \
322 "fdtheader_addr_r=0x80100000\0" \
323 "kernel_addr_r=0x81000000\0" \
324 "fdt_addr_r=0x90000000\0" \
325 "load_addr=0xa0000000\0"
327 /* Initial environment variables */
328 #ifdef CONFIG_NXP_ESBC
329 #undef CONFIG_EXTRA_ENV_SETTINGS
330 #define CONFIG_EXTRA_ENV_SETTINGS \
332 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
333 "loadaddr=0x90100000\0" \
334 "kernel_addr=0x100000\0" \
335 "ramdisk_addr=0x800000\0" \
336 "ramdisk_size=0x2000000\0" \
337 "fdt_high=0xa0000000\0" \
338 "initrd_high=0xffffffffffffffff\0" \
339 "kernel_start=0x1000000\0" \
340 "kernel_load=0xa0000000\0" \
341 "kernel_size=0x2800000\0" \
342 "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x200000;" \
343 "sf read 0xa0640000 0x640000 0x4000; esbc_validate 0xa0640000;" \
344 "sf read 0xa0e00000 0xe00000 0x100000;" \
345 "sf read 0xa0680000 0x680000 0x4000;esbc_validate 0xa0680000;" \
346 "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \
347 "mcmemsize=0x70000000 \0"
348 #else /* if !(CONFIG_NXP_ESBC) */
349 #ifdef CONFIG_TFABOOT
350 #define QSPI_MC_INIT_CMD \
351 "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
352 "sf read 0x80e00000 0xE00000 0x100000;" \
353 "fsl_mc start mc 0x80a00000 0x80e00000\0"
354 #define SD_MC_INIT_CMD \
355 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
356 "mmc read 0x80e00000 0x7000 0x800;" \
357 "fsl_mc start mc 0x80a00000 0x80e00000\0"
358 #define IFC_MC_INIT_CMD \
359 "fsl_mc start mc 0x580A00000 0x580E00000\0"
361 #undef CONFIG_EXTRA_ENV_SETTINGS
362 #define CONFIG_EXTRA_ENV_SETTINGS \
364 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
365 "loadaddr=0x90100000\0" \
366 "kernel_addr=0x100000\0" \
367 "kernel_addr_sd=0x800\0" \
368 "ramdisk_addr=0x800000\0" \
369 "ramdisk_size=0x2000000\0" \
370 "fdt_high=0xa0000000\0" \
371 "initrd_high=0xffffffffffffffff\0" \
372 "kernel_start=0x1000000\0" \
373 "kernel_start_sd=0x8000\0" \
374 "kernel_load=0xa0000000\0" \
375 "kernel_size=0x2800000\0" \
376 "kernel_size_sd=0x14000\0" \
377 "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
378 "sf read 0x80e00000 0xE00000 0x100000;" \
379 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
380 "mcmemsize=0x70000000 \0" \
381 "BOARD=ls1088aqds\0" \
382 "scriptaddr=0x80000000\0" \
383 "scripthdraddr=0x80080000\0" \
385 "boot_scripts=ls1088aqds_boot.scr\0" \
386 "boot_script_hdr=hdr_ls1088aqds_bs.out\0" \
387 "scan_dev_for_boot_part=" \
388 "part list ${devtype} ${devnum} devplist; " \
389 "env exists devplist || setenv devplist 1; " \
390 "for distro_bootpart in ${devplist}; do " \
391 "if fstype ${devtype} " \
392 "${devnum}:${distro_bootpart} " \
393 "bootfstype; then " \
394 "run scan_dev_for_boot; " \
398 "load ${devtype} ${devnum}:${distro_bootpart} " \
399 "${scriptaddr} ${prefix}${script}; " \
400 "env exists secureboot && load ${devtype} " \
401 "${devnum}:${distro_bootpart} " \
402 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
403 "env exists secureboot " \
404 "&& esbc_validate ${scripthdraddr};" \
405 "source ${scriptaddr}\0" \
406 "qspi_bootcmd=echo Trying load from qspi..; " \
408 "sf read 0x80001000 0xd00000 0x100000; " \
409 "fsl_mc lazyapply dpl 0x80001000 && " \
410 "sf read $kernel_load $kernel_start " \
411 "$kernel_size && bootm $kernel_load#$BOARD\0" \
412 "sd_bootcmd=echo Trying load from sd card..; " \
413 "mmcinfo;mmc read 0x80001000 0x6800 0x800; "\
414 "fsl_mc lazyapply dpl 0x80001000 && " \
415 "mmc read $kernel_load $kernel_start_sd " \
416 "$kernel_size_sd && bootm $kernel_load#$BOARD\0" \
417 "nor_bootcmd=echo Trying load from nor..; " \
418 "fsl_mc lazyapply dpl 0x580d00000 && " \
419 "cp.b $kernel_start $kernel_load " \
420 "$kernel_size && bootm $kernel_load#$BOARD\0"
422 #if defined(CONFIG_QSPI_BOOT)
423 #undef CONFIG_EXTRA_ENV_SETTINGS
424 #define CONFIG_EXTRA_ENV_SETTINGS \
426 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
427 "loadaddr=0x90100000\0" \
428 "kernel_addr=0x100000\0" \
429 "ramdisk_addr=0x800000\0" \
430 "ramdisk_size=0x2000000\0" \
431 "fdt_high=0xa0000000\0" \
432 "initrd_high=0xffffffffffffffff\0" \
433 "kernel_start=0x1000000\0" \
434 "kernel_load=0xa0000000\0" \
435 "kernel_size=0x2800000\0" \
436 "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
437 "sf read 0x80e00000 0xE00000 0x100000;" \
438 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
439 "mcmemsize=0x70000000 \0"
440 #elif defined(CONFIG_SD_BOOT)
441 #undef CONFIG_EXTRA_ENV_SETTINGS
442 #define CONFIG_EXTRA_ENV_SETTINGS \
444 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
445 "loadaddr=0x90100000\0" \
446 "kernel_addr=0x800\0" \
447 "ramdisk_addr=0x800000\0" \
448 "ramdisk_size=0x2000000\0" \
449 "fdt_high=0xa0000000\0" \
450 "initrd_high=0xffffffffffffffff\0" \
451 "kernel_start=0x8000\0" \
452 "kernel_load=0xa0000000\0" \
453 "kernel_size=0x14000\0" \
454 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
455 "mmc read 0x80e00000 0x7000 0x800;" \
456 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
457 "mcmemsize=0x70000000 \0"
459 #undef CONFIG_EXTRA_ENV_SETTINGS
460 #define CONFIG_EXTRA_ENV_SETTINGS \
462 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
463 "loadaddr=0x90100000\0" \
464 "kernel_addr=0x100000\0" \
465 "ramdisk_addr=0x800000\0" \
466 "ramdisk_size=0x2000000\0" \
467 "fdt_high=0xa0000000\0" \
468 "initrd_high=0xffffffffffffffff\0" \
469 "kernel_start=0x1000000\0" \
470 "kernel_load=0xa0000000\0" \
471 "kernel_size=0x2800000\0" \
472 "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \
473 "mcmemsize=0x70000000 \0"
475 #endif /* CONFIG_TFABOOT */
476 #endif /* CONFIG_NXP_ESBC */
478 #ifdef CONFIG_TFABOOT
479 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
480 "env exists secureboot && esbc_halt;;"
481 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
482 "env exists secureboot && esbc_halt;;"
483 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
484 "env exists secureboot && esbc_halt;;"
487 #ifdef CONFIG_FSL_MC_ENET
488 #define CONFIG_FSL_MEMAC
489 #define RGMII_PHY1_ADDR 0x1
490 #define RGMII_PHY2_ADDR 0x2
491 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
492 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
493 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
494 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
496 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
497 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
498 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
499 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
500 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
501 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
502 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
503 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
504 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
505 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
506 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
507 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
508 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
509 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
510 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
511 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
515 #define BOOT_TARGET_DEVICES(func) \
518 func(SCSI, scsi, 0) \
520 #include <config_distro_bootcmd.h>
522 #include <asm/fsl_secure_boot.h>
524 #endif /* __LS1088A_QDS_H */