1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2020-2021 NXP
6 #ifndef __LS1088A_QDS_H
7 #define __LS1088A_QDS_H
9 #include "ls1088a_common.h"
13 unsigned long get_board_sys_clk(void);
17 #define CONFIG_MISC_INIT_R
20 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
21 #define CONFIG_QIXIS_I2C_ACCESS
24 #define CONFIG_SYS_CLK_FREQ 100000000
26 #define CONFIG_QIXIS_I2C_ACCESS
27 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
30 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
31 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
33 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
35 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
36 #define SPD_EEPROM_ADDRESS 0x51
37 #define CONFIG_SYS_SPD_BUS_NUM 0
43 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
44 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
45 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
46 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
48 #define CONFIG_SYS_NOR0_CSPR \
49 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
53 #define CONFIG_SYS_NOR0_CSPR_EARLY \
54 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
58 #define CONFIG_SYS_NOR1_CSPR \
59 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
63 #define CONFIG_SYS_NOR1_CSPR_EARLY \
64 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
68 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
69 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
70 FTIM0_NOR_TEADC(0x5) | \
71 FTIM0_NOR_TAVDS(0x6) | \
73 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
74 FTIM1_NOR_TRAD_NOR(0x1a) | \
75 FTIM1_NOR_TSEQRAD_NOR(0x13))
76 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \
77 FTIM2_NOR_TCH(0x8) | \
78 FTIM2_NOR_TWPH(0xe) | \
80 #define CONFIG_SYS_NOR_FTIM3 0x04000000
81 #define CONFIG_SYS_IFC_CCR 0x01000000
84 #define CONFIG_SYS_FLASH_QUIET_TEST
85 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
87 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
88 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
89 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
90 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
92 #define CONFIG_SYS_FLASH_EMPTY_INFO
93 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
94 CONFIG_SYS_FLASH_BASE + 0x40000000}
98 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
99 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
101 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
102 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
103 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
104 | CSPR_MSEL_NAND /* MSEL = NAND */ \
106 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
108 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
109 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
110 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
111 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
112 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
113 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
114 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
116 /* ONFI NAND Flash mode0 Timing Params */
117 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
118 FTIM0_NAND_TWP(0x18) | \
119 FTIM0_NAND_TWCHT(0x07) | \
120 FTIM0_NAND_TWH(0x0a))
121 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
122 FTIM1_NAND_TWBE(0x39) | \
123 FTIM1_NAND_TRR(0x0e) | \
124 FTIM1_NAND_TRP(0x18))
125 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
126 FTIM2_NAND_TREH(0x0a) | \
127 FTIM2_NAND_TWHRE(0x1e))
128 #define CONFIG_SYS_NAND_FTIM3 0x0
130 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
131 #define CONFIG_SYS_MAX_NAND_DEVICE 1
132 #define CONFIG_MTD_NAND_VERIFY_WRITE
134 #define CONFIG_FSL_QIXIS
135 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
136 #define QIXIS_LBMAP_SWITCH 6
137 #define QIXIS_QMAP_MASK 0xe0
138 #define QIXIS_QMAP_SHIFT 5
139 #define QIXIS_LBMAP_MASK 0x0f
140 #define QIXIS_LBMAP_SHIFT 0
141 #define QIXIS_LBMAP_DFLTBANK 0x0e
142 #define QIXIS_LBMAP_ALTBANK 0x2e
143 #define QIXIS_LBMAP_SD 0x00
144 #define QIXIS_LBMAP_EMMC 0x00
145 #define QIXIS_LBMAP_IFC 0x00
146 #define QIXIS_LBMAP_SD_QSPI 0x0e
147 #define QIXIS_LBMAP_QSPI 0x0e
148 #define QIXIS_RCW_SRC_IFC 0x25
149 #define QIXIS_RCW_SRC_SD 0x40
150 #define QIXIS_RCW_SRC_EMMC 0x41
151 #define QIXIS_RCW_SRC_QSPI 0x62
152 #define QIXIS_RST_CTL_RESET 0x41
153 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
154 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
155 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
156 #define QIXIS_RST_FORCE_MEM 0x01
157 #define QIXIS_STAT_PRES1 0xb
158 #define QIXIS_SDID_MASK 0x07
159 #define QIXIS_ESDHC_NO_ADAPTER 0x7
161 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
162 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
166 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
171 #define SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
172 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
173 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
175 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12)
177 /* QIXIS Timing parameters*/
178 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
179 FTIM0_GPCM_TEADC(0x0e) | \
180 FTIM0_GPCM_TEAHC(0x0e))
181 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
182 FTIM1_GPCM_TRAD(0x3f))
183 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
184 FTIM2_GPCM_TCH(0xf) | \
185 FTIM2_GPCM_TWP(0x3E))
186 #define SYS_FPGA_CS_FTIM3 0x0
188 #ifdef CONFIG_TFABOOT
189 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
190 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
191 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
192 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
193 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
194 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
195 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
196 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
197 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
198 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
199 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
200 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
201 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
202 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
203 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
204 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
205 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
206 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
207 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
208 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
209 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
210 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
211 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
212 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
213 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
214 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
215 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
216 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
217 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
218 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
219 #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
220 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
221 #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
222 #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
223 #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
224 #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
226 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
227 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
228 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
229 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
230 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
231 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
232 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
233 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
234 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
235 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
236 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
237 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
238 #define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK
239 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
240 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
241 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
242 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
243 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
245 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
246 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
247 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
248 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
249 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
250 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
251 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
252 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
253 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
254 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
255 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
256 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
257 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
258 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
259 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
260 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
261 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
262 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
263 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
264 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
265 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
266 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
267 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
268 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
269 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
270 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
271 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
272 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
273 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
274 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
275 #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
276 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
277 #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
278 #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
279 #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
280 #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
284 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
287 * I2C bus multiplexer
289 #define I2C_MUX_PCA_ADDR_PRI 0x77
290 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
291 #define I2C_RETIMER_ADDR 0x18
292 #define I2C_RETIMER_ADDR2 0x19
293 #define I2C_MUX_CH_DEFAULT 0x8
294 #define I2C_MUX_CH5 0xD
296 #define I2C_MUX_CH_VOL_MONITOR 0xA
298 /* Voltage monitor on channel 2*/
299 #define I2C_VOL_MONITOR_ADDR 0x63
300 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
301 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
302 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
303 #define I2C_SVDD_MONITOR_ADDR 0x4F
305 #define CONFIG_VID_FLS_ENV "ls1088aqds_vdd_mv"
308 /* The lowest and highest voltage allowed for LS1088AQDS */
309 #define VDD_MV_MIN 819
310 #define VDD_MV_MAX 1212
312 #define CONFIG_VOL_MONITOR_LTC3882_SET
313 #define CONFIG_VOL_MONITOR_LTC3882_READ
315 #define PWM_CHANNEL0 0x0
321 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
324 #define CONFIG_SYS_I2C_EEPROM_NXID
325 #define CONFIG_SYS_EEPROM_BUS_NUM 0
327 #ifdef CONFIG_FSL_DSPI
328 #define CONFIG_SPI_FLASH_STMICRO
329 #define CONFIG_SPI_FLASH_SST
330 #define CONFIG_SPI_FLASH_EON
331 #if !defined(CONFIG_TFABOOT) && \
332 !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
336 #ifdef CONFIG_SPL_BUILD
337 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
339 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
342 #define CONFIG_FSL_MEMAC
345 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
346 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
349 "kernelheader_addr_r=0x80200000\0" \
350 "fdtheader_addr_r=0x80100000\0" \
351 "kernel_addr_r=0x81000000\0" \
352 "fdt_addr_r=0x90000000\0" \
353 "load_addr=0xa0000000\0"
355 /* Initial environment variables */
356 #ifdef CONFIG_NXP_ESBC
357 #undef CONFIG_EXTRA_ENV_SETTINGS
358 #define CONFIG_EXTRA_ENV_SETTINGS \
360 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
361 "loadaddr=0x90100000\0" \
362 "kernel_addr=0x100000\0" \
363 "ramdisk_addr=0x800000\0" \
364 "ramdisk_size=0x2000000\0" \
365 "fdt_high=0xa0000000\0" \
366 "initrd_high=0xffffffffffffffff\0" \
367 "kernel_start=0x1000000\0" \
368 "kernel_load=0xa0000000\0" \
369 "kernel_size=0x2800000\0" \
370 "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x200000;" \
371 "sf read 0xa0640000 0x640000 0x4000; esbc_validate 0xa0640000;" \
372 "sf read 0xa0e00000 0xe00000 0x100000;" \
373 "sf read 0xa0680000 0x680000 0x4000;esbc_validate 0xa0680000;" \
374 "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \
375 "mcmemsize=0x70000000 \0"
376 #else /* if !(CONFIG_NXP_ESBC) */
377 #ifdef CONFIG_TFABOOT
378 #define QSPI_MC_INIT_CMD \
379 "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
380 "sf read 0x80e00000 0xE00000 0x100000;" \
381 "fsl_mc start mc 0x80a00000 0x80e00000\0"
382 #define SD_MC_INIT_CMD \
383 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
384 "mmc read 0x80e00000 0x7000 0x800;" \
385 "fsl_mc start mc 0x80a00000 0x80e00000\0"
386 #define IFC_MC_INIT_CMD \
387 "fsl_mc start mc 0x580A00000 0x580E00000\0"
389 #undef CONFIG_EXTRA_ENV_SETTINGS
390 #define CONFIG_EXTRA_ENV_SETTINGS \
392 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
393 "loadaddr=0x90100000\0" \
394 "kernel_addr=0x100000\0" \
395 "kernel_addr_sd=0x800\0" \
396 "ramdisk_addr=0x800000\0" \
397 "ramdisk_size=0x2000000\0" \
398 "fdt_high=0xa0000000\0" \
399 "initrd_high=0xffffffffffffffff\0" \
400 "kernel_start=0x1000000\0" \
401 "kernel_start_sd=0x8000\0" \
402 "kernel_load=0xa0000000\0" \
403 "kernel_size=0x2800000\0" \
404 "kernel_size_sd=0x14000\0" \
405 "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
406 "sf read 0x80e00000 0xE00000 0x100000;" \
407 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
408 "mcmemsize=0x70000000 \0" \
409 "BOARD=ls1088aqds\0" \
410 "scriptaddr=0x80000000\0" \
411 "scripthdraddr=0x80080000\0" \
413 "boot_scripts=ls1088aqds_boot.scr\0" \
414 "boot_script_hdr=hdr_ls1088aqds_bs.out\0" \
415 "scan_dev_for_boot_part=" \
416 "part list ${devtype} ${devnum} devplist; " \
417 "env exists devplist || setenv devplist 1; " \
418 "for distro_bootpart in ${devplist}; do " \
419 "if fstype ${devtype} " \
420 "${devnum}:${distro_bootpart} " \
421 "bootfstype; then " \
422 "run scan_dev_for_boot; " \
426 "load ${devtype} ${devnum}:${distro_bootpart} " \
427 "${scriptaddr} ${prefix}${script}; " \
428 "env exists secureboot && load ${devtype} " \
429 "${devnum}:${distro_bootpart} " \
430 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
431 "env exists secureboot " \
432 "&& esbc_validate ${scripthdraddr};" \
433 "source ${scriptaddr}\0" \
434 "qspi_bootcmd=echo Trying load from qspi..; " \
436 "sf read 0x80001000 0xd00000 0x100000; " \
437 "fsl_mc lazyapply dpl 0x80001000 && " \
438 "sf read $kernel_load $kernel_start " \
439 "$kernel_size && bootm $kernel_load#$BOARD\0" \
440 "sd_bootcmd=echo Trying load from sd card..; " \
441 "mmcinfo;mmc read 0x80001000 0x6800 0x800; "\
442 "fsl_mc lazyapply dpl 0x80001000 && " \
443 "mmc read $kernel_load $kernel_start_sd " \
444 "$kernel_size_sd && bootm $kernel_load#$BOARD\0" \
445 "nor_bootcmd=echo Trying load from nor..; " \
446 "fsl_mc lazyapply dpl 0x580d00000 && " \
447 "cp.b $kernel_start $kernel_load " \
448 "$kernel_size && bootm $kernel_load#$BOARD\0"
450 #if defined(CONFIG_QSPI_BOOT)
451 #undef CONFIG_EXTRA_ENV_SETTINGS
452 #define CONFIG_EXTRA_ENV_SETTINGS \
454 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
455 "loadaddr=0x90100000\0" \
456 "kernel_addr=0x100000\0" \
457 "ramdisk_addr=0x800000\0" \
458 "ramdisk_size=0x2000000\0" \
459 "fdt_high=0xa0000000\0" \
460 "initrd_high=0xffffffffffffffff\0" \
461 "kernel_start=0x1000000\0" \
462 "kernel_load=0xa0000000\0" \
463 "kernel_size=0x2800000\0" \
464 "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
465 "sf read 0x80e00000 0xE00000 0x100000;" \
466 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
467 "mcmemsize=0x70000000 \0"
468 #elif defined(CONFIG_SD_BOOT)
469 #undef CONFIG_EXTRA_ENV_SETTINGS
470 #define CONFIG_EXTRA_ENV_SETTINGS \
472 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
473 "loadaddr=0x90100000\0" \
474 "kernel_addr=0x800\0" \
475 "ramdisk_addr=0x800000\0" \
476 "ramdisk_size=0x2000000\0" \
477 "fdt_high=0xa0000000\0" \
478 "initrd_high=0xffffffffffffffff\0" \
479 "kernel_start=0x8000\0" \
480 "kernel_load=0xa0000000\0" \
481 "kernel_size=0x14000\0" \
482 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
483 "mmc read 0x80e00000 0x7000 0x800;" \
484 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
485 "mcmemsize=0x70000000 \0"
487 #undef CONFIG_EXTRA_ENV_SETTINGS
488 #define CONFIG_EXTRA_ENV_SETTINGS \
490 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
491 "loadaddr=0x90100000\0" \
492 "kernel_addr=0x100000\0" \
493 "ramdisk_addr=0x800000\0" \
494 "ramdisk_size=0x2000000\0" \
495 "fdt_high=0xa0000000\0" \
496 "initrd_high=0xffffffffffffffff\0" \
497 "kernel_start=0x1000000\0" \
498 "kernel_load=0xa0000000\0" \
499 "kernel_size=0x2800000\0" \
500 "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \
501 "mcmemsize=0x70000000 \0"
503 #endif /* CONFIG_TFABOOT */
504 #endif /* CONFIG_NXP_ESBC */
506 #ifdef CONFIG_TFABOOT
507 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
508 "env exists secureboot && esbc_halt;;"
509 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
510 "env exists secureboot && esbc_halt;;"
511 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
512 "env exists secureboot && esbc_halt;;"
515 #ifdef CONFIG_FSL_MC_ENET
516 #define CONFIG_FSL_MEMAC
517 #define RGMII_PHY1_ADDR 0x1
518 #define RGMII_PHY2_ADDR 0x2
519 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
520 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
521 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
522 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
524 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
525 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
526 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
527 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
528 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
529 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
530 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
531 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
532 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
533 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
534 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
535 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
536 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
537 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
538 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
539 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
541 #define CONFIG_ETHPRIME "DPMAC1@xgmii"
542 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
546 #define BOOT_TARGET_DEVICES(func) \
549 func(SCSI, scsi, 0) \
551 #include <config_distro_bootcmd.h>
553 #include <asm/fsl_secure_boot.h>
555 #endif /* __LS1088A_QDS_H */