1 /* SPDX-License-Identifier: GPL-2.0+ */
6 #ifndef __LS1088A_QDS_H
7 #define __LS1088A_QDS_H
9 #include "ls1088a_common.h"
13 unsigned long get_board_sys_clk(void);
14 unsigned long get_board_ddr_clk(void);
18 #define CONFIG_SYS_MMC_ENV_DEV 0
20 #define CONFIG_MISC_INIT_R
22 #define CONFIG_ENV_SIZE 0x20000
23 #define CONFIG_ENV_OFFSET 0x500000
24 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
26 #define CONFIG_ENV_SECT_SIZE 0x40000
28 #if defined(CONFIG_QSPI_BOOT)
29 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
30 #define CONFIG_ENV_SECT_SIZE 0x40000
31 #elif defined(CONFIG_SD_BOOT)
32 #define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
33 #define CONFIG_SYS_MMC_ENV_DEV 0
34 #define CONFIG_ENV_SIZE 0x2000
36 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
37 #define CONFIG_ENV_SECT_SIZE 0x20000
38 #define CONFIG_ENV_SIZE 0x20000
42 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
43 #define CONFIG_QIXIS_I2C_ACCESS
46 #undef CONFIG_CMD_IMLS
47 #define CONFIG_SYS_CLK_FREQ 100000000
48 #define CONFIG_DDR_CLK_FREQ 100000000
50 #define CONFIG_QIXIS_I2C_ACCESS
52 #define CONFIG_SYS_I2C_EARLY_INIT
54 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
55 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
58 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
59 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
61 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
63 #define CONFIG_DDR_SPD
64 #define CONFIG_DDR_ECC
65 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
66 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
67 #define SPD_EEPROM_ADDRESS 0x51
68 #define CONFIG_SYS_SPD_BUS_NUM 0
74 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
75 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
76 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
77 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
79 #define CONFIG_SYS_NOR0_CSPR \
80 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
84 #define CONFIG_SYS_NOR0_CSPR_EARLY \
85 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
89 #define CONFIG_SYS_NOR1_CSPR \
90 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
94 #define CONFIG_SYS_NOR1_CSPR_EARLY \
95 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
99 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
100 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
101 FTIM0_NOR_TEADC(0x5) | \
102 FTIM0_NOR_TAVDS(0x6) | \
103 FTIM0_NOR_TEAHC(0x5))
104 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
105 FTIM1_NOR_TRAD_NOR(0x1a) | \
106 FTIM1_NOR_TSEQRAD_NOR(0x13))
107 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \
108 FTIM2_NOR_TCH(0x8) | \
109 FTIM2_NOR_TWPH(0xe) | \
111 #define CONFIG_SYS_NOR_FTIM3 0x04000000
112 #define CONFIG_SYS_IFC_CCR 0x01000000
115 #define CONFIG_SYS_FLASH_QUIET_TEST
116 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
118 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
119 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
120 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
121 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
123 #define CONFIG_SYS_FLASH_EMPTY_INFO
124 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
125 CONFIG_SYS_FLASH_BASE + 0x40000000}
129 #define CONFIG_NAND_FSL_IFC
130 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
131 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
133 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
134 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
135 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
136 | CSPR_MSEL_NAND /* MSEL = NAND */ \
138 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
140 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
141 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
142 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
143 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
144 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
145 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
146 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
148 #define CONFIG_SYS_NAND_ONFI_DETECTION
150 /* ONFI NAND Flash mode0 Timing Params */
151 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
152 FTIM0_NAND_TWP(0x18) | \
153 FTIM0_NAND_TWCHT(0x07) | \
154 FTIM0_NAND_TWH(0x0a))
155 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
156 FTIM1_NAND_TWBE(0x39) | \
157 FTIM1_NAND_TRR(0x0e) | \
158 FTIM1_NAND_TRP(0x18))
159 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
160 FTIM2_NAND_TREH(0x0a) | \
161 FTIM2_NAND_TWHRE(0x1e))
162 #define CONFIG_SYS_NAND_FTIM3 0x0
164 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
165 #define CONFIG_SYS_MAX_NAND_DEVICE 1
166 #define CONFIG_MTD_NAND_VERIFY_WRITE
167 #define CONFIG_CMD_NAND
169 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
171 #define CONFIG_FSL_QIXIS
172 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
173 #define QIXIS_LBMAP_SWITCH 6
174 #define QIXIS_QMAP_MASK 0xe0
175 #define QIXIS_QMAP_SHIFT 5
176 #define QIXIS_LBMAP_MASK 0x0f
177 #define QIXIS_LBMAP_SHIFT 0
178 #define QIXIS_LBMAP_DFLTBANK 0x0e
179 #define QIXIS_LBMAP_ALTBANK 0x2e
180 #define QIXIS_LBMAP_SD 0x00
181 #define QIXIS_LBMAP_EMMC 0x00
182 #define QIXIS_LBMAP_IFC 0x00
183 #define QIXIS_LBMAP_SD_QSPI 0x0e
184 #define QIXIS_LBMAP_QSPI 0x0e
185 #define QIXIS_RCW_SRC_IFC 0x25
186 #define QIXIS_RCW_SRC_SD 0x40
187 #define QIXIS_RCW_SRC_EMMC 0x41
188 #define QIXIS_RCW_SRC_QSPI 0x62
189 #define QIXIS_RST_CTL_RESET 0x41
190 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
191 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
192 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
193 #define QIXIS_RST_FORCE_MEM 0x01
194 #define QIXIS_STAT_PRES1 0xb
195 #define QIXIS_SDID_MASK 0x07
196 #define QIXIS_ESDHC_NO_ADAPTER 0x7
198 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
199 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
203 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
208 #define SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
209 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
210 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
212 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12)
214 /* QIXIS Timing parameters*/
215 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
216 FTIM0_GPCM_TEADC(0x0e) | \
217 FTIM0_GPCM_TEAHC(0x0e))
218 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
219 FTIM1_GPCM_TRAD(0x3f))
220 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
221 FTIM2_GPCM_TCH(0xf) | \
222 FTIM2_GPCM_TWP(0x3E))
223 #define SYS_FPGA_CS_FTIM3 0x0
225 #ifdef CONFIG_TFABOOT
226 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
227 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
228 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
229 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
230 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
231 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
232 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
233 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
234 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
235 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
236 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
237 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
238 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
239 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
240 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
241 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
242 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
243 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
244 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
245 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
246 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
247 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
248 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
249 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
250 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
251 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
252 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
253 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
254 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
255 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
256 #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
257 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
258 #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
259 #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
260 #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
261 #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
263 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
264 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
265 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
266 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
267 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
268 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
269 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
270 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
271 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
272 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
273 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
274 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
275 #define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK
276 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
277 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
278 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
279 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
280 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
282 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
283 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
284 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
285 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
286 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
287 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
288 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
289 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
290 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
291 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
292 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
293 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
294 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
295 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
296 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
297 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
298 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
299 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
300 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
301 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
302 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
303 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
304 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
305 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
306 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
307 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
308 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
309 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
310 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
311 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
312 #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
313 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
314 #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
315 #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
316 #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
317 #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
321 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
324 * I2C bus multiplexer
326 #define I2C_MUX_PCA_ADDR_PRI 0x77
327 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
328 #define I2C_RETIMER_ADDR 0x18
329 #define I2C_RETIMER_ADDR2 0x19
330 #define I2C_MUX_CH_DEFAULT 0x8
331 #define I2C_MUX_CH5 0xD
333 #define I2C_MUX_CH_VOL_MONITOR 0xA
335 /* Voltage monitor on channel 2*/
336 #define I2C_VOL_MONITOR_ADDR 0x63
337 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
338 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
339 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
340 #define I2C_SVDD_MONITOR_ADDR 0x4F
342 #define CONFIG_VID_FLS_ENV "ls1088aqds_vdd_mv"
345 /* The lowest and highest voltage allowed for LS1088AQDS */
346 #define VDD_MV_MIN 819
347 #define VDD_MV_MAX 1212
349 #define CONFIG_VOL_MONITOR_LTC3882_SET
350 #define CONFIG_VOL_MONITOR_LTC3882_READ
352 /* PM Bus commands code for LTC3882*/
353 #define PMBUS_CMD_PAGE 0x0
354 #define PMBUS_CMD_READ_VOUT 0x8B
355 #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
356 #define PMBUS_CMD_VOUT_COMMAND 0x21
358 #define PWM_CHANNEL0 0x0
364 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
367 #define CONFIG_ID_EEPROM
368 #define CONFIG_SYS_I2C_EEPROM_NXID
369 #define CONFIG_SYS_EEPROM_BUS_NUM 0
370 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
371 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
372 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
373 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
376 #if defined(CONFIG_TFABOOT) || \
377 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
378 #define FSL_QSPI_FLASH_SIZE (1 << 26)
379 #define FSL_QSPI_FLASH_NUM 2
383 #ifdef CONFIG_FSL_DSPI
384 #define CONFIG_SPI_FLASH_STMICRO
385 #define CONFIG_SPI_FLASH_SST
386 #define CONFIG_SPI_FLASH_EON
387 #if !defined(CONFIG_TFABOOT) && \
388 !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
392 #define CONFIG_CMD_MEMINFO
393 #define CONFIG_SYS_MEMTEST_START 0x80000000
394 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
396 #ifdef CONFIG_SPL_BUILD
397 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
399 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
402 #define CONFIG_FSL_MEMAC
405 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
406 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
407 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
409 /* Initial environment variables */
410 #ifdef CONFIG_SECURE_BOOT
411 #undef CONFIG_EXTRA_ENV_SETTINGS
412 #define CONFIG_EXTRA_ENV_SETTINGS \
413 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
414 "loadaddr=0x90100000\0" \
415 "kernel_addr=0x100000\0" \
416 "ramdisk_addr=0x800000\0" \
417 "ramdisk_size=0x2000000\0" \
418 "fdt_high=0xa0000000\0" \
419 "initrd_high=0xffffffffffffffff\0" \
420 "kernel_start=0x1000000\0" \
421 "kernel_load=0xa0000000\0" \
422 "kernel_size=0x2800000\0" \
423 "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x100000;" \
424 "sf read 0xa0700000 0x700000 0x4000; esbc_validate 0xa0700000;" \
425 "sf read 0xa0e00000 0xe00000 0x100000;" \
426 "sf read 0xa0740000 0x740000 0x4000;esbc_validate 0xa0740000;" \
427 "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \
428 "mcmemsize=0x70000000 \0"
429 #else /* if !(CONFIG_SECURE_BOOT) */
430 #ifdef CONFIG_TFABOOT
431 #define QSPI_MC_INIT_CMD \
432 "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
433 "sf read 0x80100000 0xE00000 0x100000;" \
434 "fsl_mc start mc 0x80000000 0x80100000\0"
435 #define SD_MC_INIT_CMD \
436 "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
437 "mmc read 0x80100000 0x7000 0x800;" \
438 "fsl_mc start mc 0x80000000 0x80100000\0"
439 #define IFC_MC_INIT_CMD \
440 "fsl_mc start mc 0x580A00000 0x580E00000\0"
442 #undef CONFIG_EXTRA_ENV_SETTINGS
443 #define CONFIG_EXTRA_ENV_SETTINGS \
444 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
445 "loadaddr=0x90100000\0" \
446 "kernel_addr=0x100000\0" \
447 "kernel_addr_sd=0x800\0" \
448 "ramdisk_addr=0x800000\0" \
449 "ramdisk_size=0x2000000\0" \
450 "fdt_high=0xa0000000\0" \
451 "initrd_high=0xffffffffffffffff\0" \
452 "kernel_start=0x1000000\0" \
453 "kernel_start_sd=0x8000\0" \
454 "kernel_load=0xa0000000\0" \
455 "kernel_size=0x2800000\0" \
456 "kernel_size_sd=0x14000\0" \
457 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
458 "sf read 0x80100000 0xE00000 0x100000;" \
459 "fsl_mc start mc 0x80000000 0x80100000\0" \
460 "mcmemsize=0x70000000 \0"
461 #define QSPI_NOR_BOOTCOMMAND "sf probe 0:0;" \
462 "sf read 0x80001000 0xd00000 0x100000;"\
463 " fsl_mc lazyapply dpl 0x80001000 &&" \
464 " sf read $kernel_load $kernel_start" \
465 " $kernel_size && bootm $kernel_load"
466 #define SD_BOOTCOMMAND "mmcinfo;mmc read 0x80001000 0x6800 0x800;"\
467 " fsl_mc lazyapply dpl 0x80001000 &&" \
468 " mmc read $kernel_load $kernel_start_sd" \
469 " $kernel_size_sd && bootm $kernel_load"
470 #define IFC_NOR_BOOTCOMMAND "fsl_mc lazyapply dpl 0x580d00000 &&" \
471 " cp.b $kernel_start $kernel_load" \
472 " $kernel_size && bootm $kernel_load"
474 #if defined(CONFIG_QSPI_BOOT)
475 #undef CONFIG_EXTRA_ENV_SETTINGS
476 #define CONFIG_EXTRA_ENV_SETTINGS \
477 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
478 "loadaddr=0x90100000\0" \
479 "kernel_addr=0x100000\0" \
480 "ramdisk_addr=0x800000\0" \
481 "ramdisk_size=0x2000000\0" \
482 "fdt_high=0xa0000000\0" \
483 "initrd_high=0xffffffffffffffff\0" \
484 "kernel_start=0x1000000\0" \
485 "kernel_load=0xa0000000\0" \
486 "kernel_size=0x2800000\0" \
487 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
488 "sf read 0x80100000 0xE00000 0x100000;" \
489 "fsl_mc start mc 0x80000000 0x80100000\0" \
490 "mcmemsize=0x70000000 \0"
491 #elif defined(CONFIG_SD_BOOT)
492 #undef CONFIG_EXTRA_ENV_SETTINGS
493 #define CONFIG_EXTRA_ENV_SETTINGS \
494 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
495 "loadaddr=0x90100000\0" \
496 "kernel_addr=0x800\0" \
497 "ramdisk_addr=0x800000\0" \
498 "ramdisk_size=0x2000000\0" \
499 "fdt_high=0xa0000000\0" \
500 "initrd_high=0xffffffffffffffff\0" \
501 "kernel_start=0x8000\0" \
502 "kernel_load=0xa0000000\0" \
503 "kernel_size=0x14000\0" \
504 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
505 "mmc read 0x80100000 0x7000 0x800;" \
506 "fsl_mc start mc 0x80000000 0x80100000\0" \
507 "mcmemsize=0x70000000 \0"
509 #undef CONFIG_EXTRA_ENV_SETTINGS
510 #define CONFIG_EXTRA_ENV_SETTINGS \
511 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
512 "loadaddr=0x90100000\0" \
513 "kernel_addr=0x100000\0" \
514 "ramdisk_addr=0x800000\0" \
515 "ramdisk_size=0x2000000\0" \
516 "fdt_high=0xa0000000\0" \
517 "initrd_high=0xffffffffffffffff\0" \
518 "kernel_start=0x1000000\0" \
519 "kernel_load=0xa0000000\0" \
520 "kernel_size=0x2800000\0" \
521 "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \
522 "mcmemsize=0x70000000 \0"
524 #endif /* CONFIG_TFABOOT */
525 #endif /* CONFIG_SECURE_BOOT */
527 #ifdef CONFIG_FSL_MC_ENET
528 #define CONFIG_FSL_MEMAC
529 #define CONFIG_PHYLIB
530 #define CONFIG_PHYLIB_10G
531 #define CONFIG_PHY_VITESSE
532 #define CONFIG_PHY_REALTEK
533 #define CONFIG_PHY_TERANETICS
534 #define RGMII_PHY1_ADDR 0x1
535 #define RGMII_PHY2_ADDR 0x2
536 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
537 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
538 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
539 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
541 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
542 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
543 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
544 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
545 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
546 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
547 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
548 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
549 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
550 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
551 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
552 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
553 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
554 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
555 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
556 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
558 #define CONFIG_ETHPRIME "DPMAC1@xgmii"
559 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
563 #define BOOT_TARGET_DEVICES(func) \
566 func(SCSI, scsi, 0) \
568 #include <config_distro_bootcmd.h>
570 #include <asm/fsl_secure_boot.h>
572 #endif /* __LS1088A_QDS_H */