include/configs/ls1088aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2020 NXP
   4  */
   5
   6 #ifndef __LS1088A_QDS_H
   7 #define __LS1088A_QDS_H
   8
   9 #include "ls1088a_common.h"
  10
  11
  12 #ifndef __ASSEMBLY__
  13 unsigned long get_board_sys_clk(void);
  14 unsigned long get_board_ddr_clk(void);
  15 #endif
  16
  17 #ifdef CONFIG_TFABOOT
  18 #define CONFIG_SYS_MMC_ENV_DEV          0
  19
  20 #define CONFIG_MISC_INIT_R
  21 #else
  22 #if defined(CONFIG_QSPI_BOOT)
  23 #elif defined(CONFIG_SD_BOOT)
  24 #define CONFIG_SYS_MMC_ENV_DEV          0
  25 #endif
  26 #endif
  27
  28 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  29 #define CONFIG_QIXIS_I2C_ACCESS
  30 #define SYS_NO_FLASH
  31
  32 #undef CONFIG_CMD_IMLS
  33 #define CONFIG_SYS_CLK_FREQ             100000000
  34 #define CONFIG_DDR_CLK_FREQ             100000000
  35 #else
  36 #define CONFIG_QIXIS_I2C_ACCESS
  37 #ifndef CONFIG_DM_I2C
  38 #define CONFIG_SYS_I2C_EARLY_INIT
  39 #endif
  40 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  41 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
  42 #endif
  43
  44 #define COUNTER_FREQUENCY_REAL          (CONFIG_SYS_CLK_FREQ/4)
  45 #define COUNTER_FREQUENCY               25000000        /* 25MHz */
  46
  47 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  48
  49 #define CONFIG_DDR_SPD
  50 #define CONFIG_DDR_ECC
  51 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  52 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  53 #define SPD_EEPROM_ADDRESS              0x51
  54 #define CONFIG_SYS_SPD_BUS_NUM          0
  55
  56
  57 /*
  58  * IFC Definitions
  59  */
  60 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  61 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  62 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  63 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
  64
  65 #define CONFIG_SYS_NOR0_CSPR                                    \
  66         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  67         CSPR_PORT_SIZE_16                                       | \
  68         CSPR_MSEL_NOR                                           | \
  69         CSPR_V)
  70 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  71         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  72         CSPR_PORT_SIZE_16                                       | \
  73         CSPR_MSEL_NOR                                           | \
  74         CSPR_V)
  75 #define CONFIG_SYS_NOR1_CSPR                                    \
  76         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)            | \
  77         CSPR_PORT_SIZE_16                                       | \
  78         CSPR_MSEL_NOR                                           | \
  79         CSPR_V)
  80 #define CONFIG_SYS_NOR1_CSPR_EARLY                              \
  81         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)      | \
  82         CSPR_PORT_SIZE_16                                       | \
  83         CSPR_MSEL_NOR                                           | \
  84         CSPR_V)
  85 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
  86 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
  87                                 FTIM0_NOR_TEADC(0x5) | \
  88                                 FTIM0_NOR_TAVDS(0x6) | \
  89                                 FTIM0_NOR_TEAHC(0x5))
  90 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
  91                                 FTIM1_NOR_TRAD_NOR(0x1a) | \
  92                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
  93 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x8) | \
  94                                 FTIM2_NOR_TCH(0x8) | \
  95                                 FTIM2_NOR_TWPH(0xe) | \
  96                                 FTIM2_NOR_TWP(0x1c))
  97 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  98 #define CONFIG_SYS_IFC_CCR      0x01000000
  99
 100 #ifndef SYS_NO_FLASH
 101 #define CONFIG_SYS_FLASH_QUIET_TEST
 102 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 103
 104 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 105 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 106 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 107 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 108
 109 #define CONFIG_SYS_FLASH_EMPTY_INFO
 110 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
 111                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
 112 #endif
 113 #endif
 114
 115 #define CONFIG_NAND_FSL_IFC
 116 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 117 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 118
 119 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 120 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 121                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 122                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 123                                 | CSPR_V)
 124 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 125
 126 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 127                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 128                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 129                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 130                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 131                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 132                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 133
 134 #define CONFIG_SYS_NAND_ONFI_DETECTION
 135
 136 /* ONFI NAND Flash mode0 Timing Params */
 137 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 138                                         FTIM0_NAND_TWP(0x18)   | \
 139                                         FTIM0_NAND_TWCHT(0x07) | \
 140                                         FTIM0_NAND_TWH(0x0a))
 141 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 142                                         FTIM1_NAND_TWBE(0x39)  | \
 143                                         FTIM1_NAND_TRR(0x0e)   | \
 144                                         FTIM1_NAND_TRP(0x18))
 145 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 146                                         FTIM2_NAND_TREH(0x0a) | \
 147                                         FTIM2_NAND_TWHRE(0x1e))
 148 #define CONFIG_SYS_NAND_FTIM3           0x0
 149
 150 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 151 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 152 #define CONFIG_MTD_NAND_VERIFY_WRITE
 153 #define CONFIG_CMD_NAND
 154
 155 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 156
 157 #define CONFIG_FSL_QIXIS
 158 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 159 #define QIXIS_LBMAP_SWITCH              6
 160 #define QIXIS_QMAP_MASK                 0xe0
 161 #define QIXIS_QMAP_SHIFT                5
 162 #define QIXIS_LBMAP_MASK                0x0f
 163 #define QIXIS_LBMAP_SHIFT               0
 164 #define QIXIS_LBMAP_DFLTBANK            0x0e
 165 #define QIXIS_LBMAP_ALTBANK             0x2e
 166 #define QIXIS_LBMAP_SD                  0x00
 167 #define QIXIS_LBMAP_EMMC                0x00
 168 #define QIXIS_LBMAP_IFC                 0x00
 169 #define QIXIS_LBMAP_SD_QSPI             0x0e
 170 #define QIXIS_LBMAP_QSPI                0x0e
 171 #define QIXIS_RCW_SRC_IFC               0x25
 172 #define QIXIS_RCW_SRC_SD                0x40
 173 #define QIXIS_RCW_SRC_EMMC              0x41
 174 #define QIXIS_RCW_SRC_QSPI              0x62
 175 #define QIXIS_RST_CTL_RESET             0x41
 176 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 177 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 178 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 179 #define QIXIS_RST_FORCE_MEM             0x01
 180 #define QIXIS_STAT_PRES1                0xb
 181 #define QIXIS_SDID_MASK                 0x07
 182 #define QIXIS_ESDHC_NO_ADAPTER          0x7
 183
 184 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 185 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 186                                         | CSPR_PORT_SIZE_8 \
 187                                         | CSPR_MSEL_GPCM \
 188                                         | CSPR_V)
 189 #define SYS_FPGA_CSPR_FINAL     (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 190                                         | CSPR_PORT_SIZE_8 \
 191                                         | CSPR_MSEL_GPCM \
 192                                         | CSPR_V)
 193
 194 #define SYS_FPGA_AMASK          IFC_AMASK(64 * 1024)
 195 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 196 #define CONFIG_SYS_FPGA_CSOR            CSOR_GPCM_ADM_SHIFT(0)
 197 #else
 198 #define CONFIG_SYS_FPGA_CSOR            CSOR_GPCM_ADM_SHIFT(12)
 199 #endif
 200 /* QIXIS Timing parameters*/
 201 #define SYS_FPGA_CS_FTIM0       (FTIM0_GPCM_TACSE(0x0e) | \
 202                                         FTIM0_GPCM_TEADC(0x0e) | \
 203                                         FTIM0_GPCM_TEAHC(0x0e))
 204 #define SYS_FPGA_CS_FTIM1       (FTIM1_GPCM_TACO(0xff) | \
 205                                         FTIM1_GPCM_TRAD(0x3f))
 206 #define SYS_FPGA_CS_FTIM2       (FTIM2_GPCM_TCS(0xf) | \
 207                                         FTIM2_GPCM_TCH(0xf) | \
 208                                         FTIM2_GPCM_TWP(0x3E))
 209 #define SYS_FPGA_CS_FTIM3       0x0
 210
 211 #ifdef CONFIG_TFABOOT
 212 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 213 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 214 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 215 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 216 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 217 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 218 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 219 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 220 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 221 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 222 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR_EARLY
 223 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR1_CSPR
 224 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK_EARLY
 225 #define CONFIG_SYS_AMASK1_FINAL         CONFIG_SYS_NOR_AMASK
 226 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 227 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 228 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 229 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 230 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 231 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 232 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 233 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 234 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 235 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 236 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 237 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 238 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 239 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 240 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 241 #define CONFIG_SYS_CSPR3_FINAL          SYS_FPGA_CSPR_FINAL
 242 #define CONFIG_SYS_AMASK3               SYS_FPGA_AMASK
 243 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 244 #define CONFIG_SYS_CS3_FTIM0            SYS_FPGA_CS_FTIM0
 245 #define CONFIG_SYS_CS3_FTIM1            SYS_FPGA_CS_FTIM1
 246 #define CONFIG_SYS_CS3_FTIM2            SYS_FPGA_CS_FTIM2
 247 #define CONFIG_SYS_CS3_FTIM3            SYS_FPGA_CS_FTIM3
 248 #else
 249 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 250 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 251 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 252 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 253 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 254 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 255 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 256 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 257 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 258 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 259 #define CONFIG_SYS_CSPR2                CONFIG_SYS_FPGA_CSPR
 260 #define CONFIG_SYS_CSPR2_FINAL          SYS_FPGA_CSPR_FINAL
 261 #define CONFIG_SYS_AMASK2               SYS_FPGA_AMASK
 262 #define CONFIG_SYS_CSOR2                CONFIG_SYS_FPGA_CSOR
 263 #define CONFIG_SYS_CS2_FTIM0            SYS_FPGA_CS_FTIM0
 264 #define CONFIG_SYS_CS2_FTIM1            SYS_FPGA_CS_FTIM1
 265 #define CONFIG_SYS_CS2_FTIM2            SYS_FPGA_CS_FTIM2
 266 #define CONFIG_SYS_CS2_FTIM3            SYS_FPGA_CS_FTIM3
 267 #else
 268 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 269 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 270 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 271 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 272 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 273 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 274 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 275 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 276 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 277 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 278 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR_EARLY
 279 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR1_CSPR
 280 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK_EARLY
 281 #define CONFIG_SYS_AMASK1_FINAL         CONFIG_SYS_NOR_AMASK
 282 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 283 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 284 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 285 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 286 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 287 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 288 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 289 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 290 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 291 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 292 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 293 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 294 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 295 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 296 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 297 #define CONFIG_SYS_CSPR3_FINAL          SYS_FPGA_CSPR_FINAL
 298 #define CONFIG_SYS_AMASK3               SYS_FPGA_AMASK
 299 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 300 #define CONFIG_SYS_CS3_FTIM0            SYS_FPGA_CS_FTIM0
 301 #define CONFIG_SYS_CS3_FTIM1            SYS_FPGA_CS_FTIM1
 302 #define CONFIG_SYS_CS3_FTIM2            SYS_FPGA_CS_FTIM2
 303 #define CONFIG_SYS_CS3_FTIM3            SYS_FPGA_CS_FTIM3
 304 #endif
 305 #endif
 306
 307 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 308
 309 /*
 310  * I2C bus multiplexer
 311  */
 312 #define I2C_MUX_PCA_ADDR_PRI            0x77
 313 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 314 #define I2C_RETIMER_ADDR                0x18
 315 #define I2C_RETIMER_ADDR2               0x19
 316 #define I2C_MUX_CH_DEFAULT              0x8
 317 #define I2C_MUX_CH5                     0xD
 318
 319 #define I2C_MUX_CH_VOL_MONITOR          0xA
 320
 321 /* Voltage monitor on channel 2*/
 322 #define I2C_VOL_MONITOR_ADDR           0x63
 323 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 324 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 325 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 326 #define I2C_SVDD_MONITOR_ADDR           0x4F
 327
 328 #define CONFIG_VID_FLS_ENV              "ls1088aqds_vdd_mv"
 329 #define CONFIG_VID
 330
 331 /* The lowest and highest voltage allowed for LS1088AQDS */
 332 #define VDD_MV_MIN                      819
 333 #define VDD_MV_MAX                      1212
 334
 335 #define CONFIG_VOL_MONITOR_LTC3882_SET
 336 #define CONFIG_VOL_MONITOR_LTC3882_READ
 337
 338 /* PM Bus commands code for LTC3882*/
 339 #define PMBUS_CMD_PAGE                  0x0
 340 #define PMBUS_CMD_READ_VOUT             0x8B
 341 #define PMBUS_CMD_PAGE_PLUS_WRITE       0x05
 342 #define PMBUS_CMD_VOUT_COMMAND          0x21
 343
 344 #define PWM_CHANNEL0                    0x0
 345
 346 /*
 347 * RTC configuration
 348 */
 349 #define RTC
 350 #define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
 351
 352 /* EEPROM */
 353 #define CONFIG_ID_EEPROM
 354 #define CONFIG_SYS_I2C_EEPROM_NXID
 355 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 356 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x57
 357 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 358 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 359 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 360
 361 /* QSPI device */
 362 #if defined(CONFIG_TFABOOT) || \
 363         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 364 #define FSL_QSPI_FLASH_SIZE             (1 << 26)
 365 #define FSL_QSPI_FLASH_NUM              2
 366
 367 #endif
 368
 369 #ifdef CONFIG_FSL_DSPI
 370 #define CONFIG_SPI_FLASH_STMICRO
 371 #define CONFIG_SPI_FLASH_SST
 372 #define CONFIG_SPI_FLASH_EON
 373 #if !defined(CONFIG_TFABOOT) && \
 374         !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 375 #endif
 376 #endif
 377
 378 #define CONFIG_CMD_MEMINFO
 379 #define CONFIG_SYS_MEMTEST_START        0x80000000
 380 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
 381
 382 #ifdef CONFIG_SPL_BUILD
 383 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 384 #else
 385 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 386 #endif
 387
 388 #define CONFIG_FSL_MEMAC
 389
 390 /*  MMC  */
 391 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 392 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
 393         QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
 394
 395 /* Initial environment variables */
 396 #ifdef CONFIG_NXP_ESBC
 397 #undef CONFIG_EXTRA_ENV_SETTINGS
 398 #define CONFIG_EXTRA_ENV_SETTINGS               \
 399         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 400         "loadaddr=0x90100000\0"                 \
 401         "kernel_addr=0x100000\0"                \
 402         "ramdisk_addr=0x800000\0"               \
 403         "ramdisk_size=0x2000000\0"              \
 404         "fdt_high=0xa0000000\0"                 \
 405         "initrd_high=0xffffffffffffffff\0"      \
 406         "kernel_start=0x1000000\0"              \
 407         "kernel_load=0xa0000000\0"              \
 408         "kernel_size=0x2800000\0"               \
 409         "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x100000;"  \
 410         "sf read 0xa0640000 0x640000 0x4000; esbc_validate 0xa0640000;" \
 411         "sf read 0xa0e00000 0xe00000 0x100000;" \
 412         "sf read 0xa0680000 0x680000 0x4000;esbc_validate 0xa0680000;"  \
 413         "fsl_mc start mc 0xa0a00000 0xa0e00000\0"                       \
 414         "mcmemsize=0x70000000 \0"
 415 #else /* if !(CONFIG_NXP_ESBC) */
 416 #ifdef CONFIG_TFABOOT
 417 #define QSPI_MC_INIT_CMD                                \
 418         "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;"    \
 419         "sf read 0x80100000 0xE00000 0x100000;" \
 420         "fsl_mc start mc 0x80000000 0x80100000\0"
 421 #define SD_MC_INIT_CMD                          \
 422         "mmcinfo;mmc read 0x80000000 0x5000 0x800;"  \
 423         "mmc read 0x80100000 0x7000 0x800;" \
 424         "fsl_mc start mc 0x80000000 0x80100000\0"
 425 #define IFC_MC_INIT_CMD                         \
 426         "fsl_mc start mc 0x580A00000 0x580E00000\0"
 427
 428 #undef CONFIG_EXTRA_ENV_SETTINGS
 429 #define CONFIG_EXTRA_ENV_SETTINGS               \
 430         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 431         "loadaddr=0x90100000\0"                 \
 432         "kernel_addr=0x100000\0"                \
 433         "kernel_addr_sd=0x800\0"                \
 434         "ramdisk_addr=0x800000\0"               \
 435         "ramdisk_size=0x2000000\0"              \
 436         "fdt_high=0xa0000000\0"                 \
 437         "initrd_high=0xffffffffffffffff\0"      \
 438         "kernel_start=0x1000000\0"              \
 439         "kernel_start_sd=0x8000\0"              \
 440         "kernel_load=0xa0000000\0"              \
 441         "kernel_size=0x2800000\0"               \
 442         "kernel_size_sd=0x14000\0"               \
 443         "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;"  \
 444         "sf read 0x80100000 0xE00000 0x100000;" \
 445         "fsl_mc start mc 0x80000000 0x80100000\0"       \
 446         "mcmemsize=0x70000000 \0"               \
 447         "BOARD=ls1088aqds\0" \
 448         "scriptaddr=0x80000000\0"               \
 449         "scripthdraddr=0x80080000\0"            \
 450         BOOTENV                                 \
 451         "boot_scripts=ls1088aqds_boot.scr\0"    \
 452         "boot_script_hdr=hdr_ls1088aqds_bs.out\0"       \
 453         "scan_dev_for_boot_part="               \
 454                 "part list ${devtype} ${devnum} devplist; "     \
 455                 "env exists devplist || setenv devplist 1; "    \
 456                 "for distro_bootpart in ${devplist}; do "       \
 457                         "if fstype ${devtype} "                 \
 458                                 "${devnum}:${distro_bootpart} " \
 459                                 "bootfstype; then "             \
 460                                 "run scan_dev_for_boot; "       \
 461                         "fi; "                                  \
 462                 "done\0"                                        \
 463         "boot_a_script="                                        \
 464                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 465                 "${scriptaddr} ${prefix}${script}; "            \
 466         "env exists secureboot && load ${devtype} "             \
 467                 "${devnum}:${distro_bootpart} "                 \
 468                 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
 469                 "env exists secureboot "                        \
 470                 "&& esbc_validate ${scripthdraddr};"            \
 471                 "source ${scriptaddr}\0"                        \
 472         "qspi_bootcmd=echo Trying load from qspi..; " \
 473                 "sf probe 0:0; " \
 474                 "sf read 0x80001000 0xd00000 0x100000; " \
 475                 "fsl_mc lazyapply dpl 0x80001000 && " \
 476                 "sf read $kernel_load $kernel_start " \
 477                 "$kernel_size && bootm $kernel_load#$BOARD\0" \
 478         "sd_bootcmd=echo Trying load from sd card..; " \
 479                 "mmcinfo;mmc read 0x80001000 0x6800 0x800; "\
 480                 "fsl_mc lazyapply dpl 0x80001000 && " \
 481                 "mmc read $kernel_load $kernel_start_sd " \
 482                 "$kernel_size_sd && bootm $kernel_load#$BOARD\0" \
 483         "nor_bootcmd=echo Trying load from nor..; " \
 484                 "fsl_mc lazyapply dpl 0x580d00000 && " \
 485                 "cp.b $kernel_start $kernel_load " \
 486                 "$kernel_size && bootm $kernel_load#$BOARD\0"
 487 #else
 488 #if defined(CONFIG_QSPI_BOOT)
 489 #undef CONFIG_EXTRA_ENV_SETTINGS
 490 #define CONFIG_EXTRA_ENV_SETTINGS               \
 491         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 492         "loadaddr=0x90100000\0"                 \
 493         "kernel_addr=0x100000\0"                \
 494         "ramdisk_addr=0x800000\0"               \
 495         "ramdisk_size=0x2000000\0"              \
 496         "fdt_high=0xa0000000\0"                 \
 497         "initrd_high=0xffffffffffffffff\0"      \
 498         "kernel_start=0x1000000\0"              \
 499         "kernel_load=0xa0000000\0"              \
 500         "kernel_size=0x2800000\0"               \
 501         "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;"  \
 502         "sf read 0x80100000 0xE00000 0x100000;" \
 503         "fsl_mc start mc 0x80000000 0x80100000\0"       \
 504         "mcmemsize=0x70000000 \0"
 505 #elif defined(CONFIG_SD_BOOT)
 506 #undef CONFIG_EXTRA_ENV_SETTINGS
 507 #define CONFIG_EXTRA_ENV_SETTINGS               \
 508         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 509         "loadaddr=0x90100000\0"                 \
 510         "kernel_addr=0x800\0"                \
 511         "ramdisk_addr=0x800000\0"               \
 512         "ramdisk_size=0x2000000\0"              \
 513         "fdt_high=0xa0000000\0"                 \
 514         "initrd_high=0xffffffffffffffff\0"      \
 515         "kernel_start=0x8000\0"              \
 516         "kernel_load=0xa0000000\0"              \
 517         "kernel_size=0x14000\0"               \
 518         "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;"  \
 519         "mmc read 0x80100000 0x7000 0x800;" \
 520         "fsl_mc start mc 0x80000000 0x80100000\0"       \
 521         "mcmemsize=0x70000000 \0"
 522 #else   /* NOR BOOT */
 523 #undef CONFIG_EXTRA_ENV_SETTINGS
 524 #define CONFIG_EXTRA_ENV_SETTINGS               \
 525         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 526         "loadaddr=0x90100000\0"                 \
 527         "kernel_addr=0x100000\0"                \
 528         "ramdisk_addr=0x800000\0"               \
 529         "ramdisk_size=0x2000000\0"              \
 530         "fdt_high=0xa0000000\0"                 \
 531         "initrd_high=0xffffffffffffffff\0"      \
 532         "kernel_start=0x1000000\0"              \
 533         "kernel_load=0xa0000000\0"              \
 534         "kernel_size=0x2800000\0"               \
 535         "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0"   \
 536         "mcmemsize=0x70000000 \0"
 537 #endif
 538 #endif /* CONFIG_TFABOOT */
 539 #endif /* CONFIG_NXP_ESBC */
 540
 541 #ifdef CONFIG_TFABOOT
 542 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "   \
 543                            "env exists secureboot && esbc_halt;;"
 544 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "     \
 545                            "env exists secureboot && esbc_halt;;"
 546 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "   \
 547                            "env exists secureboot && esbc_halt;;"
 548 #endif
 549
 550 #ifdef CONFIG_FSL_MC_ENET
 551 #define CONFIG_FSL_MEMAC
 552 #define CONFIG_PHYLIB
 553 #define CONFIG_PHYLIB_10G
 554 #define CONFIG_PHY_VITESSE
 555 #define CONFIG_PHY_REALTEK
 556 #define CONFIG_PHY_TERANETICS
 557 #define RGMII_PHY1_ADDR         0x1
 558 #define RGMII_PHY2_ADDR         0x2
 559 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 560 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
 561 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 562 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 563
 564 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
 565 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
 566 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
 567 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
 568 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
 569 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
 570 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
 571 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
 572 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
 573 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
 574 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
 575 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
 576 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
 577 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
 578 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
 579 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
 580
 581 #define CONFIG_ETHPRIME         "DPMAC1@xgmii"
 582 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 583
 584 #endif
 585
 586 #define BOOT_TARGET_DEVICES(func) \
 587         func(USB, usb, 0) \
 588         func(MMC, mmc, 0) \
 589         func(SCSI, scsi, 0) \
 590         func(DHCP, dhcp, na)
 591 #include <config_distro_bootcmd.h>
 592
 593 #include <asm/fsl_secure_boot.h>
 594
 595 #endif /* __LS1088A_QDS_H */