4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __LS1088A_QDS_H
8 #define __LS1088A_QDS_H
10 #include "ls1088a_common.h"
13 #define CONFIG_DISPLAY_BOARDINFO_LATE
17 unsigned long get_board_sys_clk(void);
18 unsigned long get_board_ddr_clk(void);
22 #if defined(CONFIG_QSPI_BOOT)
23 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
24 #define CONFIG_ENV_SECT_SIZE 0x40000
25 #elif defined(CONFIG_SD_BOOT)
26 #define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
27 #define CONFIG_SYS_MMC_ENV_DEV 0
28 #define CONFIG_ENV_SIZE 0x2000
30 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
31 #define CONFIG_ENV_SECT_SIZE 0x20000
32 #define CONFIG_ENV_SIZE 0x20000
35 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
36 #define CONFIG_QIXIS_I2C_ACCESS
39 #undef CONFIG_CMD_IMLS
40 #define CONFIG_SYS_CLK_FREQ 100000000
41 #define CONFIG_DDR_CLK_FREQ 100000000
43 #define CONFIG_QIXIS_I2C_ACCESS
44 #define CONFIG_SYS_I2C_EARLY_INIT
45 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
46 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
49 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
50 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
52 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
54 #define CONFIG_DDR_SPD
55 #define CONFIG_DDR_ECC
56 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
57 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
58 #define SPD_EEPROM_ADDRESS 0x51
59 #define CONFIG_SYS_SPD_BUS_NUM 0
65 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
66 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
67 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
68 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
70 #define CONFIG_SYS_NOR0_CSPR \
71 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
75 #define CONFIG_SYS_NOR0_CSPR_EARLY \
76 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
80 #define CONFIG_SYS_NOR1_CSPR \
81 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
85 #define CONFIG_SYS_NOR1_CSPR_EARLY \
86 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
90 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
91 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
92 FTIM0_NOR_TEADC(0x5) | \
93 FTIM0_NOR_TAVDS(0x6) | \
95 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
96 FTIM1_NOR_TRAD_NOR(0x1a) | \
97 FTIM1_NOR_TSEQRAD_NOR(0x13))
98 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \
99 FTIM2_NOR_TCH(0x8) | \
100 FTIM2_NOR_TWPH(0xe) | \
102 #define CONFIG_SYS_NOR_FTIM3 0x04000000
103 #define CONFIG_SYS_IFC_CCR 0x01000000
106 #define CONFIG_FLASH_CFI_DRIVER
107 #define CONFIG_SYS_FLASH_CFI
108 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
109 #define CONFIG_SYS_FLASH_QUIET_TEST
110 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
112 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
113 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
114 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
115 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
117 #define CONFIG_SYS_FLASH_EMPTY_INFO
118 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
119 CONFIG_SYS_FLASH_BASE + 0x40000000}
123 #define CONFIG_NAND_FSL_IFC
124 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
125 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
127 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
128 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
129 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
130 | CSPR_MSEL_NAND /* MSEL = NAND */ \
132 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
134 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
135 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
136 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
137 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
138 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
139 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
140 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
142 #define CONFIG_SYS_NAND_ONFI_DETECTION
144 /* ONFI NAND Flash mode0 Timing Params */
145 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
146 FTIM0_NAND_TWP(0x18) | \
147 FTIM0_NAND_TWCHT(0x07) | \
148 FTIM0_NAND_TWH(0x0a))
149 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
150 FTIM1_NAND_TWBE(0x39) | \
151 FTIM1_NAND_TRR(0x0e) | \
152 FTIM1_NAND_TRP(0x18))
153 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
154 FTIM2_NAND_TREH(0x0a) | \
155 FTIM2_NAND_TWHRE(0x1e))
156 #define CONFIG_SYS_NAND_FTIM3 0x0
158 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
159 #define CONFIG_SYS_MAX_NAND_DEVICE 1
160 #define CONFIG_MTD_NAND_VERIFY_WRITE
161 #define CONFIG_CMD_NAND
163 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
165 #define CONFIG_FSL_QIXIS
166 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
167 #define QIXIS_LBMAP_SWITCH 6
168 #define QIXIS_QMAP_MASK 0xe0
169 #define QIXIS_QMAP_SHIFT 5
170 #define QIXIS_LBMAP_MASK 0x0f
171 #define QIXIS_LBMAP_SHIFT 0
172 #define QIXIS_LBMAP_DFLTBANK 0x0e
173 #define QIXIS_LBMAP_ALTBANK 0x2e
174 #define QIXIS_LBMAP_SD 0x00
175 #define QIXIS_LBMAP_EMMC 0x00
176 #define QIXIS_LBMAP_IFC 0x00
177 #define QIXIS_LBMAP_SD_QSPI 0x0e
178 #define QIXIS_LBMAP_QSPI 0x0e
179 #define QIXIS_RCW_SRC_IFC 0x25
180 #define QIXIS_RCW_SRC_SD 0x40
181 #define QIXIS_RCW_SRC_EMMC 0x41
182 #define QIXIS_RCW_SRC_QSPI 0x62
183 #define QIXIS_RST_CTL_RESET 0x41
184 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
185 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
186 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
187 #define QIXIS_RST_FORCE_MEM 0x01
188 #define QIXIS_STAT_PRES1 0xb
189 #define QIXIS_SDID_MASK 0x07
190 #define QIXIS_ESDHC_NO_ADAPTER 0x7
192 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
193 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
197 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
202 #define SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
203 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
204 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
206 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12)
208 /* QIXIS Timing parameters*/
209 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
210 FTIM0_GPCM_TEADC(0x0e) | \
211 FTIM0_GPCM_TEAHC(0x0e))
212 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
213 FTIM1_GPCM_TRAD(0x3f))
214 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
215 FTIM2_GPCM_TCH(0xf) | \
216 FTIM2_GPCM_TWP(0x3E))
217 #define SYS_FPGA_CS_FTIM3 0x0
219 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
220 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
221 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
222 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
223 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
224 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
225 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
226 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
227 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
228 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
229 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
230 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
231 #define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK
232 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
233 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
234 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
235 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
236 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
238 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
239 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
240 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
241 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
242 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
243 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
244 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
245 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
246 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
247 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
248 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
249 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
250 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
251 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
252 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
253 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
254 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
255 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
256 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
257 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
258 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
259 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
260 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
261 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
262 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
263 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
264 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
265 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
266 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
267 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
268 #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
269 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
270 #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
271 #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
272 #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
273 #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
276 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
279 * I2C bus multiplexer
281 #define I2C_MUX_PCA_ADDR_PRI 0x77
282 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
283 #define I2C_RETIMER_ADDR 0x18
284 #define I2C_RETIMER_ADDR2 0x19
285 #define I2C_MUX_CH_DEFAULT 0x8
286 #define I2C_MUX_CH5 0xD
288 #define I2C_MUX_CH_VOL_MONITOR 0xA
290 /* Voltage monitor on channel 2*/
291 #define I2C_VOL_MONITOR_ADDR 0x63
292 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
293 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
294 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
295 #define I2C_SVDD_MONITOR_ADDR 0x4F
297 #define CONFIG_VID_FLS_ENV "ls1088aqds_vdd_mv"
300 /* The lowest and highest voltage allowed for LS1088AQDS */
301 #define VDD_MV_MIN 819
302 #define VDD_MV_MAX 1212
304 #define CONFIG_VOL_MONITOR_LTC3882_SET
305 #define CONFIG_VOL_MONITOR_LTC3882_READ
307 /* PM Bus commands code for LTC3882*/
308 #define PMBUS_CMD_PAGE 0x0
309 #define PMBUS_CMD_READ_VOUT 0x8B
310 #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
311 #define PMBUS_CMD_VOUT_COMMAND 0x21
313 #define PWM_CHANNEL0 0x0
319 #define CONFIG_RTC_PCF8563 1
320 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
321 #define CONFIG_CMD_DATE
324 #define CONFIG_ID_EEPROM
325 #define CONFIG_SYS_I2C_EEPROM_NXID
326 #define CONFIG_SYS_EEPROM_BUS_NUM 0
327 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
328 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
329 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
330 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
333 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
334 #define CONFIG_FSL_QSPI
335 #define FSL_QSPI_FLASH_SIZE (1 << 26)
336 #define FSL_QSPI_FLASH_NUM 2
340 #ifdef CONFIG_FSL_DSPI
341 #define CONFIG_SPI_FLASH_STMICRO
342 #define CONFIG_SPI_FLASH_SST
343 #define CONFIG_SPI_FLASH_EON
344 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
345 #define CONFIG_SF_DEFAULT_BUS 1
346 #define CONFIG_SF_DEFAULT_CS 0
350 #define CONFIG_CMD_MEMINFO
351 #define CONFIG_CMD_MEMTEST
352 #define CONFIG_SYS_MEMTEST_START 0x80000000
353 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
355 #ifdef CONFIG_SPL_BUILD
356 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
358 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
361 #define CONFIG_FSL_MEMAC
364 #define CONFIG_FSL_ESDHC
365 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
366 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
367 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
369 /* Initial environment variables */
370 #ifdef CONFIG_SECURE_BOOT
371 #undef CONFIG_EXTRA_ENV_SETTINGS
372 #define CONFIG_EXTRA_ENV_SETTINGS \
373 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
374 "loadaddr=0x90100000\0" \
375 "kernel_addr=0x100000\0" \
376 "ramdisk_addr=0x800000\0" \
377 "ramdisk_size=0x2000000\0" \
378 "fdt_high=0xa0000000\0" \
379 "initrd_high=0xffffffffffffffff\0" \
380 "kernel_start=0x1000000\0" \
381 "kernel_load=0xa0000000\0" \
382 "kernel_size=0x2800000\0" \
383 "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x100000;" \
384 "sf read 0xa0700000 0x700000 0x4000; esbc_validate 0xa0700000;" \
385 "sf read 0xa0e00000 0xe00000 0x100000;" \
386 "sf read 0xa0740000 0x740000 0x4000;esbc_validate 0xa0740000;" \
387 "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \
388 "mcmemsize=0x70000000 \0"
389 #else /* if !(CONFIG_SECURE_BOOT) */
390 #if defined(CONFIG_QSPI_BOOT)
391 #undef CONFIG_EXTRA_ENV_SETTINGS
392 #define CONFIG_EXTRA_ENV_SETTINGS \
393 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
394 "loadaddr=0x90100000\0" \
395 "kernel_addr=0x100000\0" \
396 "ramdisk_addr=0x800000\0" \
397 "ramdisk_size=0x2000000\0" \
398 "fdt_high=0xa0000000\0" \
399 "initrd_high=0xffffffffffffffff\0" \
400 "kernel_start=0x1000000\0" \
401 "kernel_load=0xa0000000\0" \
402 "kernel_size=0x2800000\0" \
403 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
404 "sf read 0x80100000 0xE00000 0x100000;" \
405 "fsl_mc start mc 0x80000000 0x80100000\0" \
406 "mcmemsize=0x70000000 \0"
407 #elif defined(CONFIG_SD_BOOT)
408 #undef CONFIG_EXTRA_ENV_SETTINGS
409 #define CONFIG_EXTRA_ENV_SETTINGS \
410 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
411 "loadaddr=0x90100000\0" \
412 "kernel_addr=0x800\0" \
413 "ramdisk_addr=0x800000\0" \
414 "ramdisk_size=0x2000000\0" \
415 "fdt_high=0xa0000000\0" \
416 "initrd_high=0xffffffffffffffff\0" \
417 "kernel_start=0x8000\0" \
418 "kernel_load=0xa0000000\0" \
419 "kernel_size=0x14000\0" \
420 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
421 "mmc read 0x80100000 0x7000 0x800;" \
422 "fsl_mc start mc 0x80000000 0x80100000\0" \
423 "mcmemsize=0x70000000 \0"
425 #undef CONFIG_EXTRA_ENV_SETTINGS
426 #define CONFIG_EXTRA_ENV_SETTINGS \
427 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
428 "loadaddr=0x90100000\0" \
429 "kernel_addr=0x100000\0" \
430 "ramdisk_addr=0x800000\0" \
431 "ramdisk_size=0x2000000\0" \
432 "fdt_high=0xa0000000\0" \
433 "initrd_high=0xffffffffffffffff\0" \
434 "kernel_start=0x1000000\0" \
435 "kernel_load=0xa0000000\0" \
436 "kernel_size=0x2800000\0" \
437 "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \
438 "mcmemsize=0x70000000 \0"
440 #endif /* CONFIG_SECURE_BOOT */
442 #ifdef CONFIG_FSL_MC_ENET
443 #define CONFIG_FSL_MEMAC
444 #define CONFIG_PHYLIB
445 #define CONFIG_PHYLIB_10G
446 #define CONFIG_PHY_VITESSE
447 #define CONFIG_PHY_REALTEK
448 #define CONFIG_PHY_TERANETICS
449 #define RGMII_PHY1_ADDR 0x1
450 #define RGMII_PHY2_ADDR 0x2
451 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
452 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
453 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
454 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
456 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
457 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
458 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
459 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
460 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
461 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
462 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
463 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
464 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
465 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
466 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
467 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
468 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
469 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
470 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
471 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
473 #define CONFIG_MII /* MII PHY management */
474 #define CONFIG_ETHPRIME "DPMAC1@xgmii"
475 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
479 #define BOOT_TARGET_DEVICES(func) \
482 func(SCSI, scsi, 0) \
484 #include <config_distro_bootcmd.h>
486 #include <asm/fsl_secure_boot.h>
488 #endif /* __LS1088A_QDS_H */