include/configs/ls1088aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2020-2021 NXP
   4  */
   5
   6 #ifndef __LS1088A_QDS_H
   7 #define __LS1088A_QDS_H
   8
   9 #include "ls1088a_common.h"
  10
  11 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  12 #define CONFIG_QIXIS_I2C_ACCESS
  13 #define SYS_NO_FLASH
  14 #else
  15 #define CONFIG_QIXIS_I2C_ACCESS
  16 #endif
  17
  18 #define COUNTER_FREQUENCY_REAL          (get_board_sys_clk()/4)
  19 #define COUNTER_FREQUENCY               25000000        /* 25MHz */
  20
  21 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  22
  23 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  24 #define SPD_EEPROM_ADDRESS              0x51
  25 #define CONFIG_SYS_SPD_BUS_NUM          0
  26
  27
  28 /*
  29  * IFC Definitions
  30  */
  31 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  32 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  33 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  34 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
  35
  36 #define CONFIG_SYS_NOR0_CSPR                                    \
  37         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  38         CSPR_PORT_SIZE_16                                       | \
  39         CSPR_MSEL_NOR                                           | \
  40         CSPR_V)
  41 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  42         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  43         CSPR_PORT_SIZE_16                                       | \
  44         CSPR_MSEL_NOR                                           | \
  45         CSPR_V)
  46 #define CONFIG_SYS_NOR1_CSPR                                    \
  47         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)            | \
  48         CSPR_PORT_SIZE_16                                       | \
  49         CSPR_MSEL_NOR                                           | \
  50         CSPR_V)
  51 #define CONFIG_SYS_NOR1_CSPR_EARLY                              \
  52         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)      | \
  53         CSPR_PORT_SIZE_16                                       | \
  54         CSPR_MSEL_NOR                                           | \
  55         CSPR_V)
  56 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
  57 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
  58                                 FTIM0_NOR_TEADC(0x5) | \
  59                                 FTIM0_NOR_TAVDS(0x6) | \
  60                                 FTIM0_NOR_TEAHC(0x5))
  61 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
  62                                 FTIM1_NOR_TRAD_NOR(0x1a) | \
  63                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
  64 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x8) | \
  65                                 FTIM2_NOR_TCH(0x8) | \
  66                                 FTIM2_NOR_TWPH(0xe) | \
  67                                 FTIM2_NOR_TWP(0x1c))
  68 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  69 #define CONFIG_SYS_IFC_CCR      0x01000000
  70
  71 #ifndef SYS_NO_FLASH
  72 #define CONFIG_SYS_FLASH_QUIET_TEST
  73 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
  74
  75 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  76 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  77 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  78
  79 #define CONFIG_SYS_FLASH_EMPTY_INFO
  80 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
  81                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
  82 #endif
  83 #endif
  84
  85 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
  86 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
  87
  88 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  89 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  90                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  91                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
  92                                 | CSPR_V)
  93 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
  94
  95 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  96                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  97                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
  98                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
  99                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 100                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 101                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 102
 103 /* ONFI NAND Flash mode0 Timing Params */
 104 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 105                                         FTIM0_NAND_TWP(0x18)   | \
 106                                         FTIM0_NAND_TWCHT(0x07) | \
 107                                         FTIM0_NAND_TWH(0x0a))
 108 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 109                                         FTIM1_NAND_TWBE(0x39)  | \
 110                                         FTIM1_NAND_TRR(0x0e)   | \
 111                                         FTIM1_NAND_TRP(0x18))
 112 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 113                                         FTIM2_NAND_TREH(0x0a) | \
 114                                         FTIM2_NAND_TWHRE(0x1e))
 115 #define CONFIG_SYS_NAND_FTIM3           0x0
 116
 117 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 118 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 119 #define CONFIG_MTD_NAND_VERIFY_WRITE
 120
 121 #define CONFIG_FSL_QIXIS
 122 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 123 #define QIXIS_LBMAP_SWITCH              6
 124 #define QIXIS_QMAP_MASK                 0xe0
 125 #define QIXIS_QMAP_SHIFT                5
 126 #define QIXIS_LBMAP_MASK                0x0f
 127 #define QIXIS_LBMAP_SHIFT               0
 128 #define QIXIS_LBMAP_DFLTBANK            0x0e
 129 #define QIXIS_LBMAP_ALTBANK             0x2e
 130 #define QIXIS_LBMAP_SD                  0x00
 131 #define QIXIS_LBMAP_EMMC                0x00
 132 #define QIXIS_LBMAP_IFC                 0x00
 133 #define QIXIS_LBMAP_SD_QSPI             0x0e
 134 #define QIXIS_LBMAP_QSPI                0x0e
 135 #define QIXIS_RCW_SRC_IFC               0x25
 136 #define QIXIS_RCW_SRC_SD                0x40
 137 #define QIXIS_RCW_SRC_EMMC              0x41
 138 #define QIXIS_RCW_SRC_QSPI              0x62
 139 #define QIXIS_RST_CTL_RESET             0x41
 140 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 141 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 142 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 143 #define QIXIS_RST_FORCE_MEM             0x01
 144 #define QIXIS_STAT_PRES1                0xb
 145 #define QIXIS_SDID_MASK                 0x07
 146 #define QIXIS_ESDHC_NO_ADAPTER          0x7
 147
 148 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 149 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 150                                         | CSPR_PORT_SIZE_8 \
 151                                         | CSPR_MSEL_GPCM \
 152                                         | CSPR_V)
 153 #define SYS_FPGA_CSPR_FINAL     (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 154                                         | CSPR_PORT_SIZE_8 \
 155                                         | CSPR_MSEL_GPCM \
 156                                         | CSPR_V)
 157
 158 #define SYS_FPGA_AMASK          IFC_AMASK(64 * 1024)
 159 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 160 #define CONFIG_SYS_FPGA_CSOR            CSOR_GPCM_ADM_SHIFT(0)
 161 #else
 162 #define CONFIG_SYS_FPGA_CSOR            CSOR_GPCM_ADM_SHIFT(12)
 163 #endif
 164 /* QIXIS Timing parameters*/
 165 #define SYS_FPGA_CS_FTIM0       (FTIM0_GPCM_TACSE(0x0e) | \
 166                                         FTIM0_GPCM_TEADC(0x0e) | \
 167                                         FTIM0_GPCM_TEAHC(0x0e))
 168 #define SYS_FPGA_CS_FTIM1       (FTIM1_GPCM_TACO(0xff) | \
 169                                         FTIM1_GPCM_TRAD(0x3f))
 170 #define SYS_FPGA_CS_FTIM2       (FTIM2_GPCM_TCS(0xf) | \
 171                                         FTIM2_GPCM_TCH(0xf) | \
 172                                         FTIM2_GPCM_TWP(0x3E))
 173 #define SYS_FPGA_CS_FTIM3       0x0
 174
 175 #ifdef CONFIG_TFABOOT
 176 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 177 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 178 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 179 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 180 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 181 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 182 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 183 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 184 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 185 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 186 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR_EARLY
 187 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR1_CSPR
 188 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK_EARLY
 189 #define CONFIG_SYS_AMASK1_FINAL         CONFIG_SYS_NOR_AMASK
 190 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 191 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 192 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 193 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 194 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 195 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 196 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 197 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 198 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 199 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 200 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 201 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 202 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 203 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 204 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 205 #define CONFIG_SYS_CSPR3_FINAL          SYS_FPGA_CSPR_FINAL
 206 #define CONFIG_SYS_AMASK3               SYS_FPGA_AMASK
 207 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 208 #define CONFIG_SYS_CS3_FTIM0            SYS_FPGA_CS_FTIM0
 209 #define CONFIG_SYS_CS3_FTIM1            SYS_FPGA_CS_FTIM1
 210 #define CONFIG_SYS_CS3_FTIM2            SYS_FPGA_CS_FTIM2
 211 #define CONFIG_SYS_CS3_FTIM3            SYS_FPGA_CS_FTIM3
 212 #else
 213 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 214 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 215 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 216 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 217 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 218 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 219 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 220 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 221 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 222 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 223 #define CONFIG_SYS_CSPR2                CONFIG_SYS_FPGA_CSPR
 224 #define CONFIG_SYS_CSPR2_FINAL          SYS_FPGA_CSPR_FINAL
 225 #define CONFIG_SYS_AMASK2               SYS_FPGA_AMASK
 226 #define CONFIG_SYS_CSOR2                CONFIG_SYS_FPGA_CSOR
 227 #define CONFIG_SYS_CS2_FTIM0            SYS_FPGA_CS_FTIM0
 228 #define CONFIG_SYS_CS2_FTIM1            SYS_FPGA_CS_FTIM1
 229 #define CONFIG_SYS_CS2_FTIM2            SYS_FPGA_CS_FTIM2
 230 #define CONFIG_SYS_CS2_FTIM3            SYS_FPGA_CS_FTIM3
 231 #else
 232 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 233 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 234 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 235 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 236 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 237 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 238 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 239 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 240 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 241 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 242 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR_EARLY
 243 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR1_CSPR
 244 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK_EARLY
 245 #define CONFIG_SYS_AMASK1_FINAL         CONFIG_SYS_NOR_AMASK
 246 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 247 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 248 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 249 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 250 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 251 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 252 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 253 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 254 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 255 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 256 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 257 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 258 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 259 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 260 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 261 #define CONFIG_SYS_CSPR3_FINAL          SYS_FPGA_CSPR_FINAL
 262 #define CONFIG_SYS_AMASK3               SYS_FPGA_AMASK
 263 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 264 #define CONFIG_SYS_CS3_FTIM0            SYS_FPGA_CS_FTIM0
 265 #define CONFIG_SYS_CS3_FTIM1            SYS_FPGA_CS_FTIM1
 266 #define CONFIG_SYS_CS3_FTIM2            SYS_FPGA_CS_FTIM2
 267 #define CONFIG_SYS_CS3_FTIM3            SYS_FPGA_CS_FTIM3
 268 #endif
 269 #endif
 270
 271 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 272
 273 /*
 274  * I2C bus multiplexer
 275  */
 276 #define I2C_MUX_PCA_ADDR_PRI            0x77
 277 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 278 #define I2C_RETIMER_ADDR                0x18
 279 #define I2C_RETIMER_ADDR2               0x19
 280 #define I2C_MUX_CH_DEFAULT              0x8
 281 #define I2C_MUX_CH5                     0xD
 282
 283 #define I2C_MUX_CH_VOL_MONITOR          0xA
 284
 285 /* Voltage monitor on channel 2*/
 286 #define I2C_VOL_MONITOR_ADDR           0x63
 287 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 288 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 289 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 290 #define I2C_SVDD_MONITOR_ADDR           0x4F
 291
 292 /* The lowest and highest voltage allowed for LS1088AQDS */
 293 #define VDD_MV_MIN                      819
 294 #define VDD_MV_MAX                      1212
 295
 296 #define PWM_CHANNEL0                    0x0
 297
 298 /*
 299 * RTC configuration
 300 */
 301 #define RTC
 302 #define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
 303
 304 /* EEPROM */
 305 #define CONFIG_SYS_I2C_EEPROM_NXID
 306 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 307
 308 #ifdef CONFIG_FSL_DSPI
 309 #if !defined(CONFIG_TFABOOT) && \
 310         !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 311 #endif
 312 #endif
 313
 314 #ifdef CONFIG_SPL_BUILD
 315 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 316 #else
 317 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 318 #endif
 319
 320 #define CONFIG_FSL_MEMAC
 321
 322 /*  MMC  */
 323 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
 324         QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
 325
 326 #define COMMON_ENV \
 327         "kernelheader_addr_r=0x80200000\0"      \
 328         "fdtheader_addr_r=0x80100000\0"         \
 329         "kernel_addr_r=0x81000000\0"            \
 330         "fdt_addr_r=0x90000000\0"               \
 331         "load_addr=0xa0000000\0"
 332
 333 /* Initial environment variables */
 334 #ifdef CONFIG_NXP_ESBC
 335 #undef CONFIG_EXTRA_ENV_SETTINGS
 336 #define CONFIG_EXTRA_ENV_SETTINGS               \
 337         COMMON_ENV                              \
 338         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 339         "loadaddr=0x90100000\0"                 \
 340         "kernel_addr=0x100000\0"                \
 341         "ramdisk_addr=0x800000\0"               \
 342         "ramdisk_size=0x2000000\0"              \
 343         "fdt_high=0xa0000000\0"                 \
 344         "initrd_high=0xffffffffffffffff\0"      \
 345         "kernel_start=0x1000000\0"              \
 346         "kernel_load=0xa0000000\0"              \
 347         "kernel_size=0x2800000\0"               \
 348         "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x200000;"  \
 349         "sf read 0xa0640000 0x640000 0x4000; esbc_validate 0xa0640000;" \
 350         "sf read 0xa0e00000 0xe00000 0x100000;" \
 351         "sf read 0xa0680000 0x680000 0x4000;esbc_validate 0xa0680000;"  \
 352         "fsl_mc start mc 0xa0a00000 0xa0e00000\0"                       \
 353         "mcmemsize=0x70000000 \0"
 354 #else /* if !(CONFIG_NXP_ESBC) */
 355 #ifdef CONFIG_TFABOOT
 356 #define QSPI_MC_INIT_CMD                                \
 357         "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"    \
 358         "sf read 0x80e00000 0xE00000 0x100000;" \
 359         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 360 #define SD_MC_INIT_CMD                          \
 361         "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
 362         "mmc read 0x80e00000 0x7000 0x800;" \
 363         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 364 #define IFC_MC_INIT_CMD                         \
 365         "fsl_mc start mc 0x580A00000 0x580E00000\0"
 366
 367 #undef CONFIG_EXTRA_ENV_SETTINGS
 368 #define CONFIG_EXTRA_ENV_SETTINGS               \
 369         COMMON_ENV                              \
 370         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 371         "loadaddr=0x90100000\0"                 \
 372         "kernel_addr=0x100000\0"                \
 373         "kernel_addr_sd=0x800\0"                \
 374         "ramdisk_addr=0x800000\0"               \
 375         "ramdisk_size=0x2000000\0"              \
 376         "fdt_high=0xa0000000\0"                 \
 377         "initrd_high=0xffffffffffffffff\0"      \
 378         "kernel_start=0x1000000\0"              \
 379         "kernel_start_sd=0x8000\0"              \
 380         "kernel_load=0xa0000000\0"              \
 381         "kernel_size=0x2800000\0"               \
 382         "kernel_size_sd=0x14000\0"               \
 383         "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"  \
 384         "sf read 0x80e00000 0xE00000 0x100000;" \
 385         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 386         "mcmemsize=0x70000000 \0"               \
 387         "BOARD=ls1088aqds\0" \
 388         "scriptaddr=0x80000000\0"               \
 389         "scripthdraddr=0x80080000\0"            \
 390         BOOTENV                                 \
 391         "boot_scripts=ls1088aqds_boot.scr\0"    \
 392         "boot_script_hdr=hdr_ls1088aqds_bs.out\0"       \
 393         "scan_dev_for_boot_part="               \
 394                 "part list ${devtype} ${devnum} devplist; "     \
 395                 "env exists devplist || setenv devplist 1; "    \
 396                 "for distro_bootpart in ${devplist}; do "       \
 397                         "if fstype ${devtype} "                 \
 398                                 "${devnum}:${distro_bootpart} " \
 399                                 "bootfstype; then "             \
 400                                 "run scan_dev_for_boot; "       \
 401                         "fi; "                                  \
 402                 "done\0"                                        \
 403         "boot_a_script="                                        \
 404                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 405                 "${scriptaddr} ${prefix}${script}; "            \
 406         "env exists secureboot && load ${devtype} "             \
 407                 "${devnum}:${distro_bootpart} "                 \
 408                 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
 409                 "env exists secureboot "                        \
 410                 "&& esbc_validate ${scripthdraddr};"            \
 411                 "source ${scriptaddr}\0"                        \
 412         "qspi_bootcmd=echo Trying load from qspi..; " \
 413                 "sf probe 0:0; " \
 414                 "sf read 0x80001000 0xd00000 0x100000; " \
 415                 "fsl_mc lazyapply dpl 0x80001000 && " \
 416                 "sf read $kernel_load $kernel_start " \
 417                 "$kernel_size && bootm $kernel_load#$BOARD\0" \
 418         "sd_bootcmd=echo Trying load from sd card..; " \
 419                 "mmcinfo;mmc read 0x80001000 0x6800 0x800; "\
 420                 "fsl_mc lazyapply dpl 0x80001000 && " \
 421                 "mmc read $kernel_load $kernel_start_sd " \
 422                 "$kernel_size_sd && bootm $kernel_load#$BOARD\0" \
 423         "nor_bootcmd=echo Trying load from nor..; " \
 424                 "fsl_mc lazyapply dpl 0x580d00000 && " \
 425                 "cp.b $kernel_start $kernel_load " \
 426                 "$kernel_size && bootm $kernel_load#$BOARD\0"
 427 #else
 428 #if defined(CONFIG_QSPI_BOOT)
 429 #undef CONFIG_EXTRA_ENV_SETTINGS
 430 #define CONFIG_EXTRA_ENV_SETTINGS               \
 431         COMMON_ENV                              \
 432         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 433         "loadaddr=0x90100000\0"                 \
 434         "kernel_addr=0x100000\0"                \
 435         "ramdisk_addr=0x800000\0"               \
 436         "ramdisk_size=0x2000000\0"              \
 437         "fdt_high=0xa0000000\0"                 \
 438         "initrd_high=0xffffffffffffffff\0"      \
 439         "kernel_start=0x1000000\0"              \
 440         "kernel_load=0xa0000000\0"              \
 441         "kernel_size=0x2800000\0"               \
 442         "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"  \
 443         "sf read 0x80e00000 0xE00000 0x100000;" \
 444         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 445         "mcmemsize=0x70000000 \0"
 446 #elif defined(CONFIG_SD_BOOT)
 447 #undef CONFIG_EXTRA_ENV_SETTINGS
 448 #define CONFIG_EXTRA_ENV_SETTINGS               \
 449         COMMON_ENV                              \
 450         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 451         "loadaddr=0x90100000\0"                 \
 452         "kernel_addr=0x800\0"                \
 453         "ramdisk_addr=0x800000\0"               \
 454         "ramdisk_size=0x2000000\0"              \
 455         "fdt_high=0xa0000000\0"                 \
 456         "initrd_high=0xffffffffffffffff\0"      \
 457         "kernel_start=0x8000\0"              \
 458         "kernel_load=0xa0000000\0"              \
 459         "kernel_size=0x14000\0"               \
 460         "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
 461         "mmc read 0x80e00000 0x7000 0x800;" \
 462         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 463         "mcmemsize=0x70000000 \0"
 464 #else   /* NOR BOOT */
 465 #undef CONFIG_EXTRA_ENV_SETTINGS
 466 #define CONFIG_EXTRA_ENV_SETTINGS               \
 467         COMMON_ENV                              \
 468         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 469         "loadaddr=0x90100000\0"                 \
 470         "kernel_addr=0x100000\0"                \
 471         "ramdisk_addr=0x800000\0"               \
 472         "ramdisk_size=0x2000000\0"              \
 473         "fdt_high=0xa0000000\0"                 \
 474         "initrd_high=0xffffffffffffffff\0"      \
 475         "kernel_start=0x1000000\0"              \
 476         "kernel_load=0xa0000000\0"              \
 477         "kernel_size=0x2800000\0"               \
 478         "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0"   \
 479         "mcmemsize=0x70000000 \0"
 480 #endif
 481 #endif /* CONFIG_TFABOOT */
 482 #endif /* CONFIG_NXP_ESBC */
 483
 484 #ifdef CONFIG_TFABOOT
 485 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "   \
 486                            "env exists secureboot && esbc_halt;;"
 487 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "     \
 488                            "env exists secureboot && esbc_halt;;"
 489 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "   \
 490                            "env exists secureboot && esbc_halt;;"
 491 #endif
 492
 493 #ifdef CONFIG_FSL_MC_ENET
 494 #define CONFIG_FSL_MEMAC
 495 #define RGMII_PHY1_ADDR         0x1
 496 #define RGMII_PHY2_ADDR         0x2
 497 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 498 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
 499 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 500 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 501
 502 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
 503 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
 504 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
 505 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
 506 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
 507 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
 508 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
 509 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
 510 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
 511 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
 512 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
 513 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
 514 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
 515 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
 516 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
 517 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
 518
 519 #define CONFIG_ETHPRIME         "DPMAC1@xgmii"
 520
 521 #endif
 522
 523 #define BOOT_TARGET_DEVICES(func) \
 524         func(USB, usb, 0) \
 525         func(MMC, mmc, 0) \
 526         func(SCSI, scsi, 0) \
 527         func(DHCP, dhcp, na)
 528 #include <config_distro_bootcmd.h>
 529
 530 #include <asm/fsl_secure_boot.h>
 531
 532 #endif /* __LS1088A_QDS_H */