1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017-2018 NXP
6 #ifndef __LS1088_COMMON_H
7 #define __LS1088_COMMON_H
10 #ifdef CONFIG_SPL_BUILD
11 #define SPL_NO_BOARDINFO
20 #undef CONFIG_DISPLAY_CPUINFO
23 #define CONFIG_REMAKE_ELF
25 #include <asm/arch/stream_id_lsch3.h>
26 #include <asm/arch/config.h>
27 #include <asm/arch/soc.h>
29 #define LS1088ARDB_PB_BOARD 0x4A
30 /* Link Definitions */
32 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
34 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
37 /* Link Definitions */
38 #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
40 #define CONFIG_VERY_BIG_RAM
41 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
42 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
43 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
44 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
45 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
49 #define CPU_RELEASE_ADDR secondary_boot_addr
53 #ifndef CONFIG_MPC8XXX_GPIO
54 #define CONFIG_MPC8XXX_GPIO
62 #define CONFIG_SYS_NS16550_SERIAL
63 #define CONFIG_SYS_NS16550_REG_SIZE 1
64 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
66 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
68 #if !defined(SPL_NO_IFC) || defined(CONFIG_TARGET_LS1088AQDS)
70 #define CONFIG_FSL_IFC
74 * During booting, IFC is mapped at the region of 0x30000000.
75 * But this region is limited to 256MB. To accommodate NOR, promjet
76 * and FPGA. This region is divided as below:
77 * 0x30000000 - 0x37ffffff : 128MB : NOR flash
78 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
79 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
81 * To accommodate bigger NOR flash and other devices, we will map IFC
82 * chip selects to as below:
83 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
84 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
85 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
86 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
87 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
89 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
90 * CONFIG_SYS_FLASH_BASE has the final address (core view)
91 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
92 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
93 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
96 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL
97 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
98 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
100 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
101 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
104 unsigned long long get_qixis_addr(void);
107 #define QIXIS_BASE get_qixis_addr()
108 #define QIXIS_BASE_PHYS 0x20000000
109 #define QIXIS_BASE_PHYS_EARLY 0xC000000
112 #define CONFIG_SYS_NAND_BASE 0x530000000ULL
113 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
117 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
118 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
119 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
120 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
121 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
122 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
123 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
125 /* Define phy_reset function to boot the MC based on mcinitcmd.
126 * This happens late enough to properly fixup u-boot env MAC addresses.
128 #define CONFIG_RESET_PHY_R
131 * Carve out a DDR region which will not be used by u-boot/Linux
133 * It will be used by MC and Debug Server. The MC region must be
134 * 512MB aligned, so the min size to hide is 512MB.
137 #if defined(CONFIG_FSL_MC_ENET)
138 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
141 /* Miscellaneous configurable options */
145 #define CONFIG_SCSI_AHCI_PLAT
146 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
148 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
149 #define CONFIG_SYS_SCSI_MAX_LUN 1
150 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
151 CONFIG_SYS_SCSI_MAX_LUN)
154 /* Physical Memory Map */
155 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
157 #define CONFIG_HWCONFIG
158 #define HWCONFIG_BUFFER_SIZE 128
160 /* #define CONFIG_DISPLAY_CPUINFO */
163 /* Initial environment variables */
164 #define CONFIG_EXTRA_ENV_SETTINGS \
165 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
166 "loadaddr=0x80100000\0" \
167 "kernel_addr=0x100000\0" \
168 "ramdisk_addr=0x800000\0" \
169 "ramdisk_size=0x2000000\0" \
170 "fdt_high=0xa0000000\0" \
171 "initrd_high=0xffffffffffffffff\0" \
172 "kernel_start=0x581000000\0" \
173 "kernel_load=0xa0000000\0" \
174 "kernel_size=0x2800000\0" \
175 "console=ttyAMA0,38400n8\0" \
176 "mcinitcmd=fsl_mc start mc 0x580a00000" \
179 #ifndef CONFIG_TFABOOT
180 #if defined(CONFIG_QSPI_BOOT)
181 #define CONFIG_BOOTCOMMAND "sf probe 0:0;" \
182 "sf read 0x80001000 0xd00000 0x100000;"\
183 " fsl_mc lazyapply dpl 0x80001000 &&" \
184 " sf read $kernel_load $kernel_start" \
185 " $kernel_size && bootm $kernel_load"
186 #elif defined(CONFIG_SD_BOOT)
187 #define CONFIG_BOOTCOMMAND "mmcinfo;mmc read 0x80001000 0x6800 0x800;"\
188 " fsl_mc lazyapply dpl 0x80001000 &&" \
189 " mmc read $kernel_load $kernel_start" \
190 " $kernel_size && bootm $kernel_load"
192 #define CONFIG_BOOTCOMMAND "fsl_mc lazyapply dpl 0x580d00000 &&" \
193 " cp.b $kernel_start $kernel_load" \
194 " $kernel_size && bootm $kernel_load"
196 #endif /* CONFIG_TFABOOT */
199 /* Monitor Command Prompt */
200 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
201 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
202 sizeof(CONFIG_SYS_PROMPT) + 16)
203 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
204 #define CONFIG_SYS_MAXARGS 64 /* max command args */
207 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
208 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
209 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
210 #define CONFIG_SPL_MAX_SIZE 0x16000
211 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
212 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
214 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
215 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
217 #ifdef CONFIG_NXP_ESBC
218 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
220 * HDR would be appended at end of image and copied to DDR along
221 * with U-Boot image. Here u-boot max. size is 512K. So if binary
222 * size increases then increase this size in case of secure boot as
223 * it uses raw u-boot image instead of fit image.
225 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
227 #define CONFIG_SYS_MONITOR_LEN 0x100000
228 #endif /* ifdef CONFIG_NXP_ESBC */
231 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
233 #endif /* __LS1088_COMMON_H */