1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017-2018 NXP
6 #ifndef __LS1088_COMMON_H
7 #define __LS1088_COMMON_H
10 #ifdef CONFIG_SPL_BUILD
11 #define SPL_NO_BOARDINFO
20 #undef CONFIG_DISPLAY_CPUINFO
23 #define CONFIG_REMAKE_ELF
25 #include <asm/arch/stream_id_lsch3.h>
26 #include <asm/arch/config.h>
27 #include <asm/arch/soc.h>
29 #define LS1088ARDB_PB_BOARD 0x4A
30 /* Link Definitions */
32 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
34 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
37 /* Link Definitions */
38 #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
40 #define CONFIG_VERY_BIG_RAM
41 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
42 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
43 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
44 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
45 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
49 #define CPU_RELEASE_ADDR secondary_boot_addr
51 /* Size of malloc() pool */
52 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
56 #ifndef CONFIG_MPC8XXX_GPIO
57 #define CONFIG_MPC8XXX_GPIO
65 #define CONFIG_SYS_NS16550_SERIAL
66 #define CONFIG_SYS_NS16550_REG_SIZE 1
67 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
69 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
71 #if !defined(SPL_NO_IFC) || defined(CONFIG_TARGET_LS1088AQDS)
73 #define CONFIG_FSL_IFC
77 * During booting, IFC is mapped at the region of 0x30000000.
78 * But this region is limited to 256MB. To accommodate NOR, promjet
79 * and FPGA. This region is divided as below:
80 * 0x30000000 - 0x37ffffff : 128MB : NOR flash
81 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
82 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
84 * To accommodate bigger NOR flash and other devices, we will map IFC
85 * chip selects to as below:
86 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
87 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
88 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
89 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
90 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
92 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
93 * CONFIG_SYS_FLASH_BASE has the final address (core view)
94 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
95 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
96 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
99 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL
100 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
101 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
103 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
104 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
107 unsigned long long get_qixis_addr(void);
110 #define QIXIS_BASE get_qixis_addr()
111 #define QIXIS_BASE_PHYS 0x20000000
112 #define QIXIS_BASE_PHYS_EARLY 0xC000000
115 #define CONFIG_SYS_NAND_BASE 0x530000000ULL
116 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
120 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
121 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
122 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
123 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
124 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
125 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
126 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
128 /* Define phy_reset function to boot the MC based on mcinitcmd.
129 * This happens late enough to properly fixup u-boot env MAC addresses.
131 #define CONFIG_RESET_PHY_R
134 * Carve out a DDR region which will not be used by u-boot/Linux
136 * It will be used by MC and Debug Server. The MC region must be
137 * 512MB aligned, so the min size to hide is 512MB.
140 #if defined(CONFIG_FSL_MC_ENET)
141 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
144 /* Miscellaneous configurable options */
148 #define CONFIG_SCSI_AHCI_PLAT
149 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
151 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
152 #define CONFIG_SYS_SCSI_MAX_LUN 1
153 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
154 CONFIG_SYS_SCSI_MAX_LUN)
157 /* Physical Memory Map */
158 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
160 #define CONFIG_HWCONFIG
161 #define HWCONFIG_BUFFER_SIZE 128
163 /* #define CONFIG_DISPLAY_CPUINFO */
166 /* Initial environment variables */
167 #define CONFIG_EXTRA_ENV_SETTINGS \
168 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
169 "loadaddr=0x80100000\0" \
170 "kernel_addr=0x100000\0" \
171 "ramdisk_addr=0x800000\0" \
172 "ramdisk_size=0x2000000\0" \
173 "fdt_high=0xa0000000\0" \
174 "initrd_high=0xffffffffffffffff\0" \
175 "kernel_start=0x581000000\0" \
176 "kernel_load=0xa0000000\0" \
177 "kernel_size=0x2800000\0" \
178 "console=ttyAMA0,38400n8\0" \
179 "mcinitcmd=fsl_mc start mc 0x580a00000" \
182 #ifndef CONFIG_TFABOOT
183 #if defined(CONFIG_QSPI_BOOT)
184 #define CONFIG_BOOTCOMMAND "sf probe 0:0;" \
185 "sf read 0x80001000 0xd00000 0x100000;"\
186 " fsl_mc lazyapply dpl 0x80001000 &&" \
187 " sf read $kernel_load $kernel_start" \
188 " $kernel_size && bootm $kernel_load"
189 #elif defined(CONFIG_SD_BOOT)
190 #define CONFIG_BOOTCOMMAND "mmcinfo;mmc read 0x80001000 0x6800 0x800;"\
191 " fsl_mc lazyapply dpl 0x80001000 &&" \
192 " mmc read $kernel_load $kernel_start" \
193 " $kernel_size && bootm $kernel_load"
195 #define CONFIG_BOOTCOMMAND "fsl_mc lazyapply dpl 0x580d00000 &&" \
196 " cp.b $kernel_start $kernel_load" \
197 " $kernel_size && bootm $kernel_load"
199 #endif /* CONFIG_TFABOOT */
202 /* Monitor Command Prompt */
203 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
204 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
205 sizeof(CONFIG_SYS_PROMPT) + 16)
206 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
207 #define CONFIG_SYS_MAXARGS 64 /* max command args */
210 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
211 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
212 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
213 #define CONFIG_SPL_MAX_SIZE 0x16000
214 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
215 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
217 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
218 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
220 #ifdef CONFIG_NXP_ESBC
221 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
223 * HDR would be appended at end of image and copied to DDR along
224 * with U-Boot image. Here u-boot max. size is 512K. So if binary
225 * size increases then increase this size in case of secure boot as
226 * it uses raw u-boot image instead of fit image.
228 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
230 #define CONFIG_SYS_MONITOR_LEN 0x100000
231 #endif /* ifdef CONFIG_NXP_ESBC */
234 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
236 #endif /* __LS1088_COMMON_H */