1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017-2018 NXP
6 #ifndef __LS1088_COMMON_H
7 #define __LS1088_COMMON_H
10 #ifdef CONFIG_SPL_BUILD
11 #define SPL_NO_BOARDINFO
22 #include <asm/arch/stream_id_lsch3.h>
23 #include <asm/arch/config.h>
24 #include <asm/arch/soc.h>
26 #define LS1088ARDB_PB_BOARD 0x4A
27 /* Link Definitions */
29 /* Link Definitions */
30 #define CFG_SYS_FSL_QSPI_BASE 0x20000000
32 #define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
33 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
34 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
35 #define CFG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
39 #define CPU_RELEASE_ADDR secondary_boot_addr
47 #define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
50 * During booting, IFC is mapped at the region of 0x30000000.
51 * But this region is limited to 256MB. To accommodate NOR, promjet
52 * and FPGA. This region is divided as below:
53 * 0x30000000 - 0x37ffffff : 128MB : NOR flash
54 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
55 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
57 * To accommodate bigger NOR flash and other devices, we will map IFC
58 * chip selects to as below:
59 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
60 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
61 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
62 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
63 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
65 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
66 * CFG_SYS_FLASH_BASE has the final address (core view)
67 * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
68 * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
69 * CONFIG_TEXT_BASE is linked to 0x30000000 for booting
72 #define CFG_SYS_FLASH_BASE 0x580000000ULL
73 #define CFG_SYS_FLASH_BASE_PHYS 0x80000000
74 #define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
76 #define CFG_SYS_FLASH1_BASE_PHYS 0xC0000000
77 #define CFG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
80 unsigned long long get_qixis_addr(void);
83 #define QIXIS_BASE get_qixis_addr()
84 #define QIXIS_BASE_PHYS 0x20000000
85 #define QIXIS_BASE_PHYS_EARLY 0xC000000
88 #define CFG_SYS_NAND_BASE 0x530000000ULL
89 #define CFG_SYS_NAND_BASE_PHYS 0x30000000
93 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
94 #define CFG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
95 #define CFG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
96 #define CFG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
97 #define CFG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
98 #define CFG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
99 #define CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
102 * Carve out a DDR region which will not be used by u-boot/Linux
104 * It will be used by MC and Debug Server. The MC region must be
105 * 512MB aligned, so the min size to hide is 512MB.
108 #if defined(CONFIG_FSL_MC_ENET)
109 #define CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
112 /* Miscellaneous configurable options */
114 /* Physical Memory Map */
116 #define HWCONFIG_BUFFER_SIZE 128
119 /* Initial environment variables */
120 #define CFG_EXTRA_ENV_SETTINGS \
121 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
122 "loadaddr=0x80100000\0" \
123 "kernel_addr=0x100000\0" \
124 "ramdisk_addr=0x800000\0" \
125 "ramdisk_size=0x2000000\0" \
126 "fdt_high=0xa0000000\0" \
127 "initrd_high=0xffffffffffffffff\0" \
128 "kernel_start=0x581000000\0" \
129 "kernel_load=0xa0000000\0" \
130 "kernel_size=0x2800000\0" \
131 "console=ttyAMA0,38400n8\0" \
132 "mcinitcmd=fsl_mc start mc 0x580a00000" \
136 #endif /* __LS1088_COMMON_H */