1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017-2018 NXP
6 #ifndef __LS1088_COMMON_H
7 #define __LS1088_COMMON_H
10 #ifdef CONFIG_SPL_BUILD
11 #define SPL_NO_BOARDINFO
22 #include <asm/arch/stream_id_lsch3.h>
23 #include <asm/arch/config.h>
24 #include <asm/arch/soc.h>
26 #define LS1088ARDB_PB_BOARD 0x4A
27 /* Link Definitions */
29 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
31 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
34 /* Link Definitions */
35 #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
37 #define CONFIG_VERY_BIG_RAM
38 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
39 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
40 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
41 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
42 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
46 #define CPU_RELEASE_ADDR secondary_boot_addr
54 #define CONFIG_SYS_NS16550_SERIAL
55 #define CONFIG_SYS_NS16550_REG_SIZE 1
56 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
59 * During booting, IFC is mapped at the region of 0x30000000.
60 * But this region is limited to 256MB. To accommodate NOR, promjet
61 * and FPGA. This region is divided as below:
62 * 0x30000000 - 0x37ffffff : 128MB : NOR flash
63 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
64 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
66 * To accommodate bigger NOR flash and other devices, we will map IFC
67 * chip selects to as below:
68 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
69 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
70 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
71 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
72 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
74 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
75 * CONFIG_SYS_FLASH_BASE has the final address (core view)
76 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
77 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
78 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
81 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL
82 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
83 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
85 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
86 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
89 unsigned long long get_qixis_addr(void);
92 #define QIXIS_BASE get_qixis_addr()
93 #define QIXIS_BASE_PHYS 0x20000000
94 #define QIXIS_BASE_PHYS_EARLY 0xC000000
97 #define CONFIG_SYS_NAND_BASE 0x530000000ULL
98 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
102 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
103 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
104 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
105 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
106 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
107 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
108 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
111 * Carve out a DDR region which will not be used by u-boot/Linux
113 * It will be used by MC and Debug Server. The MC region must be
114 * 512MB aligned, so the min size to hide is 512MB.
117 #if defined(CONFIG_FSL_MC_ENET)
118 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
121 /* Miscellaneous configurable options */
125 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
128 /* Physical Memory Map */
130 #define CONFIG_HWCONFIG
131 #define HWCONFIG_BUFFER_SIZE 128
134 /* Initial environment variables */
135 #define CONFIG_EXTRA_ENV_SETTINGS \
136 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
137 "loadaddr=0x80100000\0" \
138 "kernel_addr=0x100000\0" \
139 "ramdisk_addr=0x800000\0" \
140 "ramdisk_size=0x2000000\0" \
141 "fdt_high=0xa0000000\0" \
142 "initrd_high=0xffffffffffffffff\0" \
143 "kernel_start=0x581000000\0" \
144 "kernel_load=0xa0000000\0" \
145 "kernel_size=0x2800000\0" \
146 "console=ttyAMA0,38400n8\0" \
147 "mcinitcmd=fsl_mc start mc 0x580a00000" \
152 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
153 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
154 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
156 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
157 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
159 #ifdef CONFIG_NXP_ESBC
160 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
162 * HDR would be appended at end of image and copied to DDR along
163 * with U-Boot image. Here u-boot max. size is 512K. So if binary
164 * size increases then increase this size in case of secure boot as
165 * it uses raw u-boot image instead of fit image.
167 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
169 #define CONFIG_SYS_MONITOR_LEN 0x100000
170 #endif /* ifdef CONFIG_NXP_ESBC */
173 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
175 #endif /* __LS1088_COMMON_H */