1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017-2018 NXP
6 #ifndef __LS1088_COMMON_H
7 #define __LS1088_COMMON_H
10 #ifdef CONFIG_SPL_BUILD
11 #define SPL_NO_BOARDINFO
20 #undef CONFIG_DISPLAY_CPUINFO
23 #define CONFIG_REMAKE_ELF
25 #include <asm/arch/stream_id_lsch3.h>
26 #include <asm/arch/config.h>
27 #include <asm/arch/soc.h>
29 #define LS1088ARDB_PB_BOARD 0x4A
30 /* Link Definitions */
32 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
34 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
37 /* Link Definitions */
38 #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
40 #define CONFIG_SKIP_LOWLEVEL_INIT
42 #define CONFIG_VERY_BIG_RAM
43 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
44 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
45 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
46 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
47 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
51 #define CPU_RELEASE_ADDR secondary_boot_addr
53 /* Size of malloc() pool */
54 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
58 #ifndef CONFIG_MPC8XXX_GPIO
59 #define CONFIG_MPC8XXX_GPIO
67 #define CONFIG_SYS_NS16550_SERIAL
68 #define CONFIG_SYS_NS16550_REG_SIZE 1
69 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
71 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
73 #if !defined(SPL_NO_IFC) || defined(CONFIG_TARGET_LS1088AQDS)
75 #define CONFIG_FSL_IFC
79 * During booting, IFC is mapped at the region of 0x30000000.
80 * But this region is limited to 256MB. To accommodate NOR, promjet
81 * and FPGA. This region is divided as below:
82 * 0x30000000 - 0x37ffffff : 128MB : NOR flash
83 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
84 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
86 * To accommodate bigger NOR flash and other devices, we will map IFC
87 * chip selects to as below:
88 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
89 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
90 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
91 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
92 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
94 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
95 * CONFIG_SYS_FLASH_BASE has the final address (core view)
96 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
97 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
98 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
101 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL
102 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
103 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
105 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
106 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
109 unsigned long long get_qixis_addr(void);
112 #define QIXIS_BASE get_qixis_addr()
113 #define QIXIS_BASE_PHYS 0x20000000
114 #define QIXIS_BASE_PHYS_EARLY 0xC000000
117 #define CONFIG_SYS_NAND_BASE 0x530000000ULL
118 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
122 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
123 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
124 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
125 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
126 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
127 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
128 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
130 /* Define phy_reset function to boot the MC based on mcinitcmd.
131 * This happens late enough to properly fixup u-boot env MAC addresses.
133 #define CONFIG_RESET_PHY_R
136 * Carve out a DDR region which will not be used by u-boot/Linux
138 * It will be used by MC and Debug Server. The MC region must be
139 * 512MB aligned, so the min size to hide is 512MB.
142 #if defined(CONFIG_FSL_MC_ENET)
143 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
146 /* Miscellaneous configurable options */
150 #define CONFIG_SCSI_AHCI_PLAT
151 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
153 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
154 #define CONFIG_SYS_SCSI_MAX_LUN 1
155 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
156 CONFIG_SYS_SCSI_MAX_LUN)
159 /* Physical Memory Map */
160 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
162 #define CONFIG_HWCONFIG
163 #define HWCONFIG_BUFFER_SIZE 128
165 /* #define CONFIG_DISPLAY_CPUINFO */
168 /* Initial environment variables */
169 #define CONFIG_EXTRA_ENV_SETTINGS \
170 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
171 "loadaddr=0x80100000\0" \
172 "kernel_addr=0x100000\0" \
173 "ramdisk_addr=0x800000\0" \
174 "ramdisk_size=0x2000000\0" \
175 "fdt_high=0xa0000000\0" \
176 "initrd_high=0xffffffffffffffff\0" \
177 "kernel_start=0x581000000\0" \
178 "kernel_load=0xa0000000\0" \
179 "kernel_size=0x2800000\0" \
180 "console=ttyAMA0,38400n8\0" \
181 "mcinitcmd=fsl_mc start mc 0x580a00000" \
184 #ifndef CONFIG_TFABOOT
185 #if defined(CONFIG_QSPI_BOOT)
186 #define CONFIG_BOOTCOMMAND "sf probe 0:0;" \
187 "sf read 0x80001000 0xd00000 0x100000;"\
188 " fsl_mc lazyapply dpl 0x80001000 &&" \
189 " sf read $kernel_load $kernel_start" \
190 " $kernel_size && bootm $kernel_load"
191 #elif defined(CONFIG_SD_BOOT)
192 #define CONFIG_BOOTCOMMAND "mmcinfo;mmc read 0x80001000 0x6800 0x800;"\
193 " fsl_mc lazyapply dpl 0x80001000 &&" \
194 " mmc read $kernel_load $kernel_start" \
195 " $kernel_size && bootm $kernel_load"
197 #define CONFIG_BOOTCOMMAND "fsl_mc lazyapply dpl 0x580d00000 &&" \
198 " cp.b $kernel_start $kernel_load" \
199 " $kernel_size && bootm $kernel_load"
201 #endif /* CONFIG_TFABOOT */
204 /* Monitor Command Prompt */
205 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
206 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
207 sizeof(CONFIG_SYS_PROMPT) + 16)
208 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
209 #define CONFIG_SYS_MAXARGS 64 /* max command args */
212 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
213 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
214 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
215 #define CONFIG_SPL_MAX_SIZE 0x16000
216 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
217 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
219 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
220 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
222 #ifdef CONFIG_NXP_ESBC
223 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
225 * HDR would be appended at end of image and copied to DDR along
226 * with U-Boot image. Here u-boot max. size is 512K. So if binary
227 * size increases then increase this size in case of secure boot as
228 * it uses raw u-boot image instead of fit image.
230 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
232 #define CONFIG_SYS_MONITOR_LEN 0x100000
233 #endif /* ifdef CONFIG_NXP_ESBC */
236 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
238 #endif /* __LS1088_COMMON_H */