1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017-2018 NXP
6 #ifndef __LS1088_COMMON_H
7 #define __LS1088_COMMON_H
10 #ifdef CONFIG_SPL_BUILD
11 #define SPL_NO_BOARDINFO
20 #undef CONFIG_DISPLAY_CPUINFO
23 #define CONFIG_REMAKE_ELF
24 #define CONFIG_FSL_LAYERSCAPE
26 #include <asm/arch/stream_id_lsch3.h>
27 #include <asm/arch/config.h>
28 #include <asm/arch/soc.h>
30 #define LS1088ARDB_PB_BOARD 0x4A
31 /* Link Definitions */
33 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
35 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
38 /* Link Definitions */
40 #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
42 #ifdef CONFIG_QSPI_BOOT
43 #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
44 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
45 #define CONFIG_ENV_ADDR (CONFIG_SYS_FSL_QSPI_BASE + \
50 #define CONFIG_SKIP_LOWLEVEL_INIT
52 #if !defined(CONFIG_SD_BOOT)
53 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
56 #define CONFIG_VERY_BIG_RAM
57 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
58 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
59 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
60 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
61 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
65 #define CPU_RELEASE_ADDR secondary_boot_func
68 #define CONFIG_CMD_PCI
71 /* Size of malloc() pool */
72 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
75 #define CONFIG_SYS_I2C
78 #define CONFIG_SYS_NS16550_SERIAL
79 #define CONFIG_SYS_NS16550_REG_SIZE 1
80 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
82 #define CONFIG_BAUDRATE 115200
83 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
85 #if !defined(SPL_NO_IFC) || defined(CONFIG_TARGET_LS1088AQDS)
87 #define CONFIG_FSL_IFC
91 * During booting, IFC is mapped at the region of 0x30000000.
92 * But this region is limited to 256MB. To accommodate NOR, promjet
93 * and FPGA. This region is divided as below:
94 * 0x30000000 - 0x37ffffff : 128MB : NOR flash
95 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
96 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
98 * To accommodate bigger NOR flash and other devices, we will map IFC
99 * chip selects to as below:
100 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
101 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
102 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
103 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
104 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
106 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
107 * CONFIG_SYS_FLASH_BASE has the final address (core view)
108 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
109 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
110 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
113 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL
114 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
115 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
117 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
118 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
121 unsigned long long get_qixis_addr(void);
124 #define QIXIS_BASE get_qixis_addr()
125 #define QIXIS_BASE_PHYS 0x20000000
126 #define QIXIS_BASE_PHYS_EARLY 0xC000000
129 #define CONFIG_SYS_NAND_BASE 0x530000000ULL
130 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
134 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
135 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
136 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
137 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
138 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
139 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
140 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
142 /* Define phy_reset function to boot the MC based on mcinitcmd.
143 * This happens late enough to properly fixup u-boot env MAC addresses.
145 #define CONFIG_RESET_PHY_R
148 * Carve out a DDR region which will not be used by u-boot/Linux
150 * It will be used by MC and Debug Server. The MC region must be
151 * 512MB aligned, so the min size to hide is 512MB.
154 #if defined(CONFIG_FSL_MC_ENET)
155 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
157 /* Command line configuration */
158 #define CONFIG_CMD_CACHE
160 /* Miscellaneous configurable options */
161 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
165 #define CONFIG_SCSI_AHCI_PLAT
166 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
168 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
169 #define CONFIG_SYS_SCSI_MAX_LUN 1
170 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
171 CONFIG_SYS_SCSI_MAX_LUN)
174 /* Physical Memory Map */
175 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
177 #define CONFIG_HWCONFIG
178 #define HWCONFIG_BUFFER_SIZE 128
180 /* #define CONFIG_DISPLAY_CPUINFO */
183 /* Allow to overwrite serial and ethaddr */
184 #define CONFIG_ENV_OVERWRITE
186 /* Initial environment variables */
187 #define CONFIG_EXTRA_ENV_SETTINGS \
188 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
189 "loadaddr=0x80100000\0" \
190 "kernel_addr=0x100000\0" \
191 "ramdisk_addr=0x800000\0" \
192 "ramdisk_size=0x2000000\0" \
193 "fdt_high=0xa0000000\0" \
194 "initrd_high=0xffffffffffffffff\0" \
195 "kernel_start=0x581000000\0" \
196 "kernel_load=0xa0000000\0" \
197 "kernel_size=0x2800000\0" \
198 "console=ttyAMA0,38400n8\0" \
199 "mcinitcmd=fsl_mc start mc 0x580a00000" \
202 #ifndef CONFIG_TFABOOT
203 #if defined(CONFIG_QSPI_BOOT)
204 #define CONFIG_BOOTCOMMAND "sf probe 0:0;" \
205 "sf read 0x80001000 0xd00000 0x100000;"\
206 " fsl_mc lazyapply dpl 0x80001000 &&" \
207 " sf read $kernel_load $kernel_start" \
208 " $kernel_size && bootm $kernel_load"
209 #elif defined(CONFIG_SD_BOOT)
210 #define CONFIG_BOOTCOMMAND "mmcinfo;mmc read 0x80001000 0x6800 0x800;"\
211 " fsl_mc lazyapply dpl 0x80001000 &&" \
212 " mmc read $kernel_load $kernel_start" \
213 " $kernel_size && bootm $kernel_load"
215 #define CONFIG_BOOTCOMMAND "fsl_mc lazyapply dpl 0x580d00000 &&" \
216 " cp.b $kernel_start $kernel_load" \
217 " $kernel_size && bootm $kernel_load"
219 #endif /* CONFIG_TFABOOT */
222 /* Monitor Command Prompt */
223 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
224 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
225 sizeof(CONFIG_SYS_PROMPT) + 16)
226 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
227 #define CONFIG_SYS_MAXARGS 64 /* max command args */
230 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
231 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
232 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
233 #define CONFIG_SPL_MAX_SIZE 0x16000
234 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
235 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
236 #define CONFIG_SPL_TEXT_BASE 0x1800a000
238 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
239 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
241 #ifdef CONFIG_SECURE_BOOT
242 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
244 * HDR would be appended at end of image and copied to DDR along
245 * with U-Boot image. Here u-boot max. size is 512K. So if binary
246 * size increases then increase this size in case of secure boot as
247 * it uses raw u-boot image instead of fit image.
249 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
251 #define CONFIG_SYS_MONITOR_LEN 0x100000
252 #endif /* ifdef CONFIG_SECURE_BOOT */
255 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
257 #endif /* __LS1088_COMMON_H */