include/configs/ls1046ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2016 Freescale Semiconductor
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __LS1046ARDB_H__
   8 #define __LS1046ARDB_H__
   9
  10 #include "ls1046a_common.h"
  11
  12 #define CONFIG_SYS_CLK_FREQ             100000000
  13
  14 #define CONFIG_LAYERSCAPE_NS_ACCESS
  15
  16 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  17 /* Physical Memory Map */
  18 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  19
  20 #define SPD_EEPROM_ADDRESS              0x51
  21 #define CONFIG_SYS_SPD_BUS_NUM          0
  22
  23 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  24
  25 #if defined(CONFIG_QSPI_BOOT)
  26 #define CONFIG_SYS_UBOOT_BASE           0x40100000
  27 #define CONFIG_SYS_SPL_ARGS_ADDR        0x90000000
  28 #endif
  29
  30 #ifndef SPL_NO_IFC
  31 /* IFC */
  32 #define CONFIG_FSL_IFC
  33 /*
  34  * NAND Flash Definitions
  35  */
  36 #define CONFIG_NAND_FSL_IFC
  37 #endif
  38
  39 #define CONFIG_SYS_NAND_BASE            0x7e800000
  40 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
  41
  42 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  43 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  44                                 | CSPR_PORT_SIZE_8      \
  45                                 | CSPR_MSEL_NAND        \
  46                                 | CSPR_V)
  47 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
  48 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  49                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  50                                 | CSOR_NAND_ECC_MODE_8  /* 8-bit ECC */ \
  51                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
  52                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
  53                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
  54                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
  55
  56 #define CONFIG_SYS_NAND_ONFI_DETECTION
  57
  58 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
  59                                         FTIM0_NAND_TWP(0x18)   | \
  60                                         FTIM0_NAND_TWCHT(0x7) | \
  61                                         FTIM0_NAND_TWH(0xa))
  62 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
  63                                         FTIM1_NAND_TWBE(0x39)  | \
  64                                         FTIM1_NAND_TRR(0xe)   | \
  65                                         FTIM1_NAND_TRP(0x18))
  66 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
  67                                         FTIM2_NAND_TREH(0xa) | \
  68                                         FTIM2_NAND_TWHRE(0x1e))
  69 #define CONFIG_SYS_NAND_FTIM3           0x0
  70
  71 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
  72 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  73 #define CONFIG_MTD_NAND_VERIFY_WRITE
  74
  75 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
  76
  77 /*
  78  * CPLD
  79  */
  80 #define CONFIG_SYS_CPLD_BASE            0x7fb00000
  81 #define CPLD_BASE_PHYS                  CONFIG_SYS_CPLD_BASE
  82
  83 #define CONFIG_SYS_CPLD_CSPR_EXT        (0x0)
  84 #define CONFIG_SYS_CPLD_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
  85                                         CSPR_PORT_SIZE_8 | \
  86                                         CSPR_MSEL_GPCM | \
  87                                         CSPR_V)
  88 #define CONFIG_SYS_CPLD_AMASK           IFC_AMASK(64 * 1024)
  89 #define CONFIG_SYS_CPLD_CSOR            CSOR_NOR_ADM_SHIFT(16)
  90
  91 /* CPLD Timing parameters for IFC GPCM */
  92 #define CONFIG_SYS_CPLD_FTIM0           (FTIM0_GPCM_TACSE(0x0e) | \
  93                                         FTIM0_GPCM_TEADC(0x0e) | \
  94                                         FTIM0_GPCM_TEAHC(0x0e))
  95 #define CONFIG_SYS_CPLD_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
  96                                         FTIM1_GPCM_TRAD(0x3f))
  97 #define CONFIG_SYS_CPLD_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
  98                                         FTIM2_GPCM_TCH(0xf) | \
  99                                         FTIM2_GPCM_TWP(0x3E))
 100 #define CONFIG_SYS_CPLD_FTIM3           0x0
 101
 102 /* IFC Timing Params */
 103 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 104 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 105 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 106 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 107 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 108 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 109 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 110 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 111
 112 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_CPLD_CSPR_EXT
 113 #define CONFIG_SYS_CSPR2                CONFIG_SYS_CPLD_CSPR
 114 #define CONFIG_SYS_AMASK2               CONFIG_SYS_CPLD_AMASK
 115 #define CONFIG_SYS_CSOR2                CONFIG_SYS_CPLD_CSOR
 116 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_CPLD_FTIM0
 117 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_CPLD_FTIM1
 118 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_CPLD_FTIM2
 119 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_CPLD_FTIM3
 120
 121 /* EEPROM */
 122 #define CONFIG_SYS_I2C_EEPROM_NXID
 123 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 124 #define I2C_RETIMER_ADDR                        0x18
 125
 126 /* PMIC */
 127
 128 /*
 129  * Environment
 130  */
 131 #define CONFIG_SYS_FSL_QSPI_BASE        0x40000000
 132
 133 #define AQR105_IRQ_MASK                 0x80000000
 134 /* FMan */
 135 #ifndef SPL_NO_FMAN
 136 #ifdef CONFIG_SYS_DPAA_FMAN
 137 #define RGMII_PHY1_ADDR                 0x1
 138 #define RGMII_PHY2_ADDR                 0x2
 139
 140 #define SGMII_PHY1_ADDR                 0x3
 141 #define SGMII_PHY2_ADDR                 0x4
 142
 143 #define FM1_10GEC1_PHY_ADDR             0x0
 144
 145 #define FDT_SEQ_MACADDR_FROM_ENV
 146
 147 #define CONFIG_ETHPRIME                 "FM1@DTSEC3"
 148 #endif
 149
 150 #endif
 151
 152 #ifndef SPL_NO_MISC
 153 #undef CONFIG_BOOTCOMMAND
 154 #ifdef CONFIG_TFABOOT
 155 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "   \
 156                            "env exists secureboot && esbc_halt;;"
 157 #define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; "    \
 158                            "env exists secureboot && esbc_halt;"
 159 #else
 160 #if defined(CONFIG_QSPI_BOOT)
 161 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "     \
 162                            "env exists secureboot && esbc_halt;;"
 163 #elif defined(CONFIG_SD_BOOT)
 164 #define CONFIG_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; "        \
 165                            "env exists secureboot && esbc_halt;"
 166 #endif
 167 #endif
 168 #endif
 169
 170 #include <asm/fsl_secure_boot.h>
 171
 172 #endif /* __LS1046ARDB_H__ */