2 * Copyright 2016 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __LS1046ARDB_H__
8 #define __LS1046ARDB_H__
10 #include "ls1046a_common.h"
13 #define CONFIG_SYS_TEXT_BASE 0x82000000
15 #define CONFIG_SYS_TEXT_BASE 0x40100000
18 #define CONFIG_SYS_CLK_FREQ 100000000
19 #define CONFIG_DDR_CLK_FREQ 100000000
21 #define CONFIG_LAYERSCAPE_NS_ACCESS
22 #define CONFIG_MISC_INIT_R
24 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
25 /* Physical Memory Map */
26 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
27 #define CONFIG_NR_DRAM_BANKS 2
29 #define CONFIG_DDR_SPD
30 #define SPD_EEPROM_ADDRESS 0x51
31 #define CONFIG_SYS_SPD_BUS_NUM 0
33 #define CONFIG_DDR_ECC
34 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
35 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
36 #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
38 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
41 #ifdef CONFIG_RAMBOOT_PBL
42 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
46 #ifdef CONFIG_EMMC_BOOT
47 #define CONFIG_SYS_FSL_PBL_RCW \
48 board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
50 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
56 #define CONFIG_FSL_IFC
58 * NAND Flash Definitions
60 #define CONFIG_NAND_FSL_IFC
63 #define CONFIG_SYS_NAND_BASE 0x7e800000
64 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
66 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
67 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
71 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
72 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
73 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
74 | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
75 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
76 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
77 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
78 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
80 #define CONFIG_SYS_NAND_ONFI_DETECTION
82 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
83 FTIM0_NAND_TWP(0x18) | \
84 FTIM0_NAND_TWCHT(0x7) | \
86 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
87 FTIM1_NAND_TWBE(0x39) | \
88 FTIM1_NAND_TRR(0xe) | \
90 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
91 FTIM2_NAND_TREH(0xa) | \
92 FTIM2_NAND_TWHRE(0x1e))
93 #define CONFIG_SYS_NAND_FTIM3 0x0
95 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
96 #define CONFIG_SYS_MAX_NAND_DEVICE 1
97 #define CONFIG_MTD_NAND_VERIFY_WRITE
98 #define CONFIG_CMD_NAND
100 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
105 #define CONFIG_SYS_CPLD_BASE 0x7fb00000
106 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
108 #define CONFIG_SYS_CPLD_CSPR_EXT (0x0)
109 #define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
113 #define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
114 #define CONFIG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16)
116 /* CPLD Timing parameters for IFC GPCM */
117 #define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
118 FTIM0_GPCM_TEADC(0x0e) | \
119 FTIM0_GPCM_TEAHC(0x0e))
120 #define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
121 FTIM1_GPCM_TRAD(0x3f))
122 #define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
123 FTIM2_GPCM_TCH(0xf) | \
124 FTIM2_GPCM_TWP(0x3E))
125 #define CONFIG_SYS_CPLD_FTIM3 0x0
127 /* IFC Timing Params */
128 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
129 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
130 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
131 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
132 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
133 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
134 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
135 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
137 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
138 #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
139 #define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK
140 #define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR
141 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0
142 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1
143 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
144 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
147 #define CONFIG_ID_EEPROM
148 #define CONFIG_SYS_I2C_EEPROM_NXID
149 #define CONFIG_SYS_EEPROM_BUS_NUM 0
150 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
151 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
152 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
153 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
154 #define I2C_RETIMER_ADDR 0x18
159 #define CONFIG_POWER_I2C
166 #define CONFIG_ENV_OVERWRITE
169 #if defined(CONFIG_SD_BOOT)
170 #define CONFIG_ENV_IS_IN_MMC
171 #define CONFIG_SYS_MMC_ENV_DEV 0
172 #define CONFIG_ENV_OFFSET (1024 * 1024)
173 #define CONFIG_ENV_SIZE 0x2000
175 #define CONFIG_ENV_IS_IN_SPI_FLASH
176 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
177 #define CONFIG_ENV_OFFSET 0x200000 /* 2MB */
178 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */
183 #ifdef CONFIG_SYS_DPAA_FMAN
184 #define CONFIG_FMAN_ENET
185 #define CONFIG_PHYLIB
186 #define CONFIG_PHYLIB_10G
187 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
189 #define CONFIG_PHY_REALTEK
190 #define CONFIG_PHY_AQUANTIA
191 #define AQR105_IRQ_MASK 0x80000000
193 #define RGMII_PHY1_ADDR 0x1
194 #define RGMII_PHY2_ADDR 0x2
196 #define SGMII_PHY1_ADDR 0x3
197 #define SGMII_PHY2_ADDR 0x4
199 #define FM1_10GEC1_PHY_ADDR 0x0
201 #define CONFIG_ETHPRIME "FM1@DTSEC3"
207 #ifdef CONFIG_FSL_QSPI
208 #define CONFIG_SPI_FLASH_SPANSION
209 #define FSL_QSPI_FLASH_SIZE (1 << 26)
210 #define FSL_QSPI_FLASH_NUM 2
211 #define CONFIG_SPI_FLASH_BAR
217 #define CONFIG_HAS_FSL_XHCI_USB
218 #ifdef CONFIG_HAS_FSL_XHCI_USB
219 #define CONFIG_USB_XHCI_HCD
220 #define CONFIG_USB_XHCI_FSL
221 #define CONFIG_USB_XHCI_DWC3
222 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3
223 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
224 #define CONFIG_CMD_USB
225 #define CONFIG_USB_STORAGE
231 #define CONFIG_LIBATA
232 #define CONFIG_SCSI_AHCI
233 #define CONFIG_SCSI_AHCI_PLAT
236 #define CONFIG_SYS_SATA AHCI_BASE_ADDR
238 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
239 #define CONFIG_SYS_SCSI_MAX_LUN 1
240 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
241 CONFIG_SYS_SCSI_MAX_LUN)
245 #define CONFIG_BOOTCOMMAND "sf probe 0:0;sf read $kernel_load" \
246 "$kernel_start $kernel_size;" \
249 #define MTDPARTS_DEFAULT "mtdparts=1550000.quadspi:1m(rcw)," \
250 "15m(u-boot),48m(kernel.itb);" \
251 "7e800000.flash:16m(nand_uboot)," \
252 "48m(nand_kernel),448m(nand_free)"
255 #include <asm/fsl_secure_boot.h>
257 #endif /* __LS1046ARDB_H__ */