configs: Finish migration of PHY_GIGE
[platform/kernel/u-boot.git] / include / configs / ls1046ardb.h
1 /*
2  * Copyright 2016 Freescale Semiconductor
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #ifndef __LS1046ARDB_H__
8 #define __LS1046ARDB_H__
9
10 #include "ls1046a_common.h"
11
12 #ifdef CONFIG_SD_BOOT
13 #define CONFIG_SYS_TEXT_BASE            0x82000000
14 #else
15 #define CONFIG_SYS_TEXT_BASE            0x40100000
16 #endif
17
18 #define CONFIG_SYS_CLK_FREQ             100000000
19 #define CONFIG_DDR_CLK_FREQ             100000000
20
21 #define CONFIG_LAYERSCAPE_NS_ACCESS
22 #define CONFIG_MISC_INIT_R
23
24 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
25 /* Physical Memory Map */
26 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
27 #define CONFIG_NR_DRAM_BANKS            2
28
29 #define CONFIG_DDR_SPD
30 #define SPD_EEPROM_ADDRESS              0x51
31 #define CONFIG_SYS_SPD_BUS_NUM          0
32
33 #define CONFIG_DDR_ECC
34 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
35 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
36 #define CONFIG_FSL_DDR_BIST     /* enable built-in memory test */
37 #ifndef CONFIG_SPL
38 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
39 #endif
40
41 #ifdef CONFIG_RAMBOOT_PBL
42 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
43 #endif
44
45 #ifdef CONFIG_SD_BOOT
46 #ifdef CONFIG_EMMC_BOOT
47 #define CONFIG_SYS_FSL_PBL_RCW \
48         board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
49 #else
50 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
51 #endif
52 #endif
53
54 #ifndef SPL_NO_IFC
55 /* IFC */
56 #define CONFIG_FSL_IFC
57 /*
58  * NAND Flash Definitions
59  */
60 #define CONFIG_NAND_FSL_IFC
61 #endif
62
63 #define CONFIG_SYS_NAND_BASE            0x7e800000
64 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
65
66 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
67 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
68                                 | CSPR_PORT_SIZE_8      \
69                                 | CSPR_MSEL_NAND        \
70                                 | CSPR_V)
71 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
72 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
73                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
74                                 | CSOR_NAND_ECC_MODE_8  /* 8-bit ECC */ \
75                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
76                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
77                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
78                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
79
80 #define CONFIG_SYS_NAND_ONFI_DETECTION
81
82 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
83                                         FTIM0_NAND_TWP(0x18)   | \
84                                         FTIM0_NAND_TWCHT(0x7) | \
85                                         FTIM0_NAND_TWH(0xa))
86 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
87                                         FTIM1_NAND_TWBE(0x39)  | \
88                                         FTIM1_NAND_TRR(0xe)   | \
89                                         FTIM1_NAND_TRP(0x18))
90 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
91                                         FTIM2_NAND_TREH(0xa) | \
92                                         FTIM2_NAND_TWHRE(0x1e))
93 #define CONFIG_SYS_NAND_FTIM3           0x0
94
95 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
96 #define CONFIG_SYS_MAX_NAND_DEVICE      1
97 #define CONFIG_MTD_NAND_VERIFY_WRITE
98
99 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
100
101 /*
102  * CPLD
103  */
104 #define CONFIG_SYS_CPLD_BASE            0x7fb00000
105 #define CPLD_BASE_PHYS                  CONFIG_SYS_CPLD_BASE
106
107 #define CONFIG_SYS_CPLD_CSPR_EXT        (0x0)
108 #define CONFIG_SYS_CPLD_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
109                                         CSPR_PORT_SIZE_8 | \
110                                         CSPR_MSEL_GPCM | \
111                                         CSPR_V)
112 #define CONFIG_SYS_CPLD_AMASK           IFC_AMASK(64 * 1024)
113 #define CONFIG_SYS_CPLD_CSOR            CSOR_NOR_ADM_SHIFT(16)
114
115 /* CPLD Timing parameters for IFC GPCM */
116 #define CONFIG_SYS_CPLD_FTIM0           (FTIM0_GPCM_TACSE(0x0e) | \
117                                         FTIM0_GPCM_TEADC(0x0e) | \
118                                         FTIM0_GPCM_TEAHC(0x0e))
119 #define CONFIG_SYS_CPLD_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
120                                         FTIM1_GPCM_TRAD(0x3f))
121 #define CONFIG_SYS_CPLD_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
122                                         FTIM2_GPCM_TCH(0xf) | \
123                                         FTIM2_GPCM_TWP(0x3E))
124 #define CONFIG_SYS_CPLD_FTIM3           0x0
125
126 /* IFC Timing Params */
127 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
128 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
129 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
130 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
131 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
132 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
133 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
134 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
135
136 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_CPLD_CSPR_EXT
137 #define CONFIG_SYS_CSPR2                CONFIG_SYS_CPLD_CSPR
138 #define CONFIG_SYS_AMASK2               CONFIG_SYS_CPLD_AMASK
139 #define CONFIG_SYS_CSOR2                CONFIG_SYS_CPLD_CSOR
140 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_CPLD_FTIM0
141 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_CPLD_FTIM1
142 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_CPLD_FTIM2
143 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_CPLD_FTIM3
144
145 /* EEPROM */
146 #define CONFIG_ID_EEPROM
147 #define CONFIG_SYS_I2C_EEPROM_NXID
148 #define CONFIG_SYS_EEPROM_BUS_NUM               0
149 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x53
150 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
151 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
152 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
153 #define I2C_RETIMER_ADDR                        0x18
154
155 /* PMIC */
156 #define CONFIG_POWER
157 #ifdef CONFIG_POWER
158 #define CONFIG_POWER_I2C
159 #endif
160
161 /*
162  * Environment
163  */
164 #ifndef SPL_NO_ENV
165 #define CONFIG_ENV_OVERWRITE
166 #endif
167
168 #if defined(CONFIG_SD_BOOT)
169 #define CONFIG_SYS_MMC_ENV_DEV          0
170 #define CONFIG_ENV_OFFSET               (3 * 1024 * 1024)
171 #define CONFIG_ENV_SIZE                 0x2000
172 #else
173 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
174 #define CONFIG_ENV_OFFSET               0x300000        /* 3MB */
175 #define CONFIG_ENV_SECT_SIZE            0x40000         /* 256KB */
176 #endif
177
178 #define AQR105_IRQ_MASK                 0x80000000
179 /* FMan */
180 #ifndef SPL_NO_FMAN
181
182 #ifdef CONFIG_NET
183 #define CONFIG_PHY_REALTEK
184 #endif
185
186 #ifdef CONFIG_SYS_DPAA_FMAN
187 #define CONFIG_FMAN_ENET
188 #define CONFIG_PHY_AQUANTIA
189 #define CONFIG_PHYLIB_10G
190 #define RGMII_PHY1_ADDR                 0x1
191 #define RGMII_PHY2_ADDR                 0x2
192
193 #define SGMII_PHY1_ADDR                 0x3
194 #define SGMII_PHY2_ADDR                 0x4
195
196 #define FM1_10GEC1_PHY_ADDR             0x0
197
198 #define CONFIG_ETHPRIME                 "FM1@DTSEC3"
199 #endif
200
201 #endif
202
203 /* QSPI device */
204 #ifndef SPL_NO_QSPI
205 #ifdef CONFIG_FSL_QSPI
206 #define CONFIG_SPI_FLASH_SPANSION
207 #define FSL_QSPI_FLASH_SIZE             (1 << 26)
208 #define FSL_QSPI_FLASH_NUM              2
209 #endif
210 #endif
211
212 /* USB */
213 #ifndef SPL_NO_USB
214 #define CONFIG_HAS_FSL_XHCI_USB
215 #ifdef CONFIG_HAS_FSL_XHCI_USB
216 #define CONFIG_USB_XHCI_HCD
217 #define CONFIG_USB_XHCI_FSL
218 #define CONFIG_USB_XHCI_DWC3
219 #define CONFIG_USB_MAX_CONTROLLER_COUNT         3
220 #define CONFIG_USB_STORAGE
221 #endif
222 #endif
223
224 /* SATA */
225 #ifndef SPL_NO_SATA
226 #define CONFIG_LIBATA
227 #define CONFIG_SCSI_AHCI
228 #define CONFIG_SCSI_AHCI_PLAT
229
230 #define CONFIG_SYS_SATA                         AHCI_BASE_ADDR
231
232 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
233 #define CONFIG_SYS_SCSI_MAX_LUN                 1
234 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
235                                                 CONFIG_SYS_SCSI_MAX_LUN)
236 #endif
237
238 #ifndef SPL_NO_MISC
239 #undef CONFIG_BOOTCOMMAND
240 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot"  \
241                            "&& esbc_halt; run qspi_bootcmd;"
242 #define MTDPARTS_DEFAULT "mtdparts=1550000.quadspi:1m(rcw)," \
243                         "15m(u-boot),48m(kernel.itb);" \
244                         "7e800000.flash:16m(nand_uboot)," \
245                         "48m(nand_kernel),448m(nand_free)"
246 #endif
247
248 #include <asm/fsl_secure_boot.h>
249
250 #endif /* __LS1046ARDB_H__ */