2 * Copyright 2016 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __LS1046ARDB_H__
8 #define __LS1046ARDB_H__
10 #include "ls1046a_common.h"
12 #if defined(CONFIG_FSL_LS_PPA)
13 #define CONFIG_SYS_LS_PPA_FW_IN_XIP
14 #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
15 #define CONFIG_SYS_LS_PPA_FW_ADDR 0x40500000
20 #define CONFIG_SYS_TEXT_BASE 0x82000000
22 #define CONFIG_SYS_TEXT_BASE 0x40100000
25 #define CONFIG_SYS_CLK_FREQ 100000000
26 #define CONFIG_DDR_CLK_FREQ 100000000
28 #define CONFIG_LAYERSCAPE_NS_ACCESS
29 #define CONFIG_MISC_INIT_R
31 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
32 /* Physical Memory Map */
33 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
34 #define CONFIG_NR_DRAM_BANKS 2
36 #define CONFIG_DDR_SPD
37 #define SPD_EEPROM_ADDRESS 0x51
38 #define CONFIG_SYS_SPD_BUS_NUM 0
40 #define CONFIG_DDR_ECC
41 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
42 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
43 #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
44 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
46 #ifdef CONFIG_RAMBOOT_PBL
47 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
51 #ifdef CONFIG_EMMC_BOOT
52 #define CONFIG_SYS_FSL_PBL_RCW \
53 board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
55 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
60 #define CONFIG_SYS_NO_FLASH
63 #define CONFIG_FSL_IFC
66 * NAND Flash Definitions
68 #define CONFIG_NAND_FSL_IFC
70 #define CONFIG_SYS_NAND_BASE 0x7e800000
71 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
73 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
74 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
78 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
79 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
80 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
81 | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
82 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
83 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
84 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
85 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
87 #define CONFIG_SYS_NAND_ONFI_DETECTION
89 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
90 FTIM0_NAND_TWP(0x18) | \
91 FTIM0_NAND_TWCHT(0x7) | \
93 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
94 FTIM1_NAND_TWBE(0x39) | \
95 FTIM1_NAND_TRR(0xe) | \
97 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
98 FTIM2_NAND_TREH(0xa) | \
99 FTIM2_NAND_TWHRE(0x1e))
100 #define CONFIG_SYS_NAND_FTIM3 0x0
102 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
103 #define CONFIG_SYS_MAX_NAND_DEVICE 1
104 #define CONFIG_MTD_NAND_VERIFY_WRITE
105 #define CONFIG_CMD_NAND
107 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
112 #define CONFIG_SYS_CPLD_BASE 0x7fb00000
113 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
115 #define CONFIG_SYS_CPLD_CSPR_EXT (0x0)
116 #define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
120 #define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
121 #define CONFIG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16)
123 /* CPLD Timing parameters for IFC GPCM */
124 #define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
125 FTIM0_GPCM_TEADC(0x0e) | \
126 FTIM0_GPCM_TEAHC(0x0e))
127 #define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
128 FTIM1_GPCM_TRAD(0x3f))
129 #define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
130 FTIM2_GPCM_TCH(0xf) | \
131 FTIM2_GPCM_TWP(0x3E))
132 #define CONFIG_SYS_CPLD_FTIM3 0x0
134 /* IFC Timing Params */
135 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
136 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
137 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
138 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
139 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
140 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
141 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
142 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
144 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
145 #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
146 #define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK
147 #define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR
148 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0
149 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1
150 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
151 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
154 #define CONFIG_ID_EEPROM
155 #define CONFIG_SYS_I2C_EEPROM_NXID
156 #define CONFIG_SYS_EEPROM_BUS_NUM 0
157 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
158 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
159 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
160 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
161 #define I2C_RETIMER_ADDR 0x18
166 #define CONFIG_POWER_I2C
172 #define CONFIG_ENV_OVERWRITE
174 #if defined(CONFIG_SD_BOOT)
175 #define CONFIG_ENV_IS_IN_MMC
176 #define CONFIG_SYS_MMC_ENV_DEV 0
177 #define CONFIG_ENV_OFFSET (1024 * 1024)
178 #define CONFIG_ENV_SIZE 0x2000
180 #define CONFIG_ENV_IS_IN_SPI_FLASH
181 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
182 #define CONFIG_ENV_OFFSET 0x200000 /* 2MB */
183 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */
187 #ifdef CONFIG_SYS_DPAA_FMAN
188 #define CONFIG_FMAN_ENET
189 #define CONFIG_PHYLIB
190 #define CONFIG_PHYLIB_10G
191 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
193 #define CONFIG_PHY_REALTEK
194 #define CONFIG_PHY_AQUANTIA
195 #define AQR105_IRQ_MASK 0x80000000
197 #define RGMII_PHY1_ADDR 0x1
198 #define RGMII_PHY2_ADDR 0x2
200 #define SGMII_PHY1_ADDR 0x3
201 #define SGMII_PHY2_ADDR 0x4
203 #define FM1_10GEC1_PHY_ADDR 0x0
205 #define CONFIG_ETHPRIME "FM1@DTSEC3"
209 #ifdef CONFIG_FSL_QSPI
210 #define CONFIG_SPI_FLASH_SPANSION
211 #define FSL_QSPI_FLASH_SIZE (1 << 26)
212 #define FSL_QSPI_FLASH_NUM 2
213 #define CONFIG_SPI_FLASH_BAR
217 #define CONFIG_HAS_FSL_XHCI_USB
218 #ifdef CONFIG_HAS_FSL_XHCI_USB
219 #define CONFIG_USB_XHCI_HCD
220 #define CONFIG_USB_XHCI_FSL
221 #define CONFIG_USB_XHCI_DWC3
222 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3
223 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
224 #define CONFIG_CMD_USB
225 #define CONFIG_USB_STORAGE
229 #define CONFIG_LIBATA
230 #define CONFIG_SCSI_AHCI
231 #define CONFIG_SCSI_AHCI_PLAT
233 #define CONFIG_DOS_PARTITION
234 #define CONFIG_BOARD_LATE_INIT
236 #define CONFIG_SYS_SATA AHCI_BASE_ADDR
238 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
239 #define CONFIG_SYS_SCSI_MAX_LUN 1
240 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
241 CONFIG_SYS_SCSI_MAX_LUN)
242 #define CONFIG_PARTITION_UUIDS
243 #define CONFIG_EFI_PARTITION
244 #define CONFIG_CMD_GPT
246 #define CONFIG_BOOTCOMMAND "sf probe 0:0;sf read $kernel_load" \
247 "$kernel_start $kernel_size;" \
250 #define MTDPARTS_DEFAULT "mtdparts=1550000.quadspi:1m(rcw)," \
251 "15m(u-boot),48m(kernel.itb);" \
252 "7e800000.flash:16m(nand_uboot)," \
253 "48m(nand_kernel),448m(nand_free)"
255 #endif /* __LS1046ARDB_H__ */