1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016 Freescale Semiconductor
6 #ifndef __LS1046ARDB_H__
7 #define __LS1046ARDB_H__
9 #include "ls1046a_common.h"
11 #define CONFIG_SYS_CLK_FREQ 100000000
12 #define CONFIG_DDR_CLK_FREQ 100000000
14 #define CONFIG_LAYERSCAPE_NS_ACCESS
15 #define CONFIG_MISC_INIT_R
17 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
18 /* Physical Memory Map */
19 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
20 #define CONFIG_NR_DRAM_BANKS 2
22 #define CONFIG_DDR_SPD
23 #define SPD_EEPROM_ADDRESS 0x51
24 #define CONFIG_SYS_SPD_BUS_NUM 0
26 #define CONFIG_DDR_ECC
27 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
28 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
29 #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
31 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
35 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
36 #ifdef CONFIG_EMMC_BOOT
37 #define CONFIG_SYS_FSL_PBL_RCW \
38 board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
40 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
42 #elif defined(CONFIG_QSPI_BOOT)
43 #define CONFIG_SYS_FSL_PBL_RCW \
44 board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg
45 #define CONFIG_SYS_FSL_PBL_PBI \
46 board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg
47 #define CONFIG_SYS_UBOOT_BASE 0x40100000
48 #define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000
53 #define CONFIG_FSL_IFC
55 * NAND Flash Definitions
57 #define CONFIG_NAND_FSL_IFC
60 #define CONFIG_SYS_NAND_BASE 0x7e800000
61 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
63 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
64 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
68 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
69 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
70 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
71 | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
72 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
73 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
74 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
75 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
77 #define CONFIG_SYS_NAND_ONFI_DETECTION
79 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
80 FTIM0_NAND_TWP(0x18) | \
81 FTIM0_NAND_TWCHT(0x7) | \
83 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
84 FTIM1_NAND_TWBE(0x39) | \
85 FTIM1_NAND_TRR(0xe) | \
87 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
88 FTIM2_NAND_TREH(0xa) | \
89 FTIM2_NAND_TWHRE(0x1e))
90 #define CONFIG_SYS_NAND_FTIM3 0x0
92 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
93 #define CONFIG_SYS_MAX_NAND_DEVICE 1
94 #define CONFIG_MTD_NAND_VERIFY_WRITE
96 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
101 #define CONFIG_SYS_CPLD_BASE 0x7fb00000
102 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
104 #define CONFIG_SYS_CPLD_CSPR_EXT (0x0)
105 #define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
109 #define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
110 #define CONFIG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16)
112 /* CPLD Timing parameters for IFC GPCM */
113 #define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
114 FTIM0_GPCM_TEADC(0x0e) | \
115 FTIM0_GPCM_TEAHC(0x0e))
116 #define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
117 FTIM1_GPCM_TRAD(0x3f))
118 #define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
119 FTIM2_GPCM_TCH(0xf) | \
120 FTIM2_GPCM_TWP(0x3E))
121 #define CONFIG_SYS_CPLD_FTIM3 0x0
123 /* IFC Timing Params */
124 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
125 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
126 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
127 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
128 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
129 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
130 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
131 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
133 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
134 #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
135 #define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK
136 #define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR
137 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0
138 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1
139 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
140 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
143 #define CONFIG_ID_EEPROM
144 #define CONFIG_SYS_I2C_EEPROM_NXID
145 #define CONFIG_SYS_EEPROM_BUS_NUM 0
146 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
147 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
148 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
149 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
150 #define I2C_RETIMER_ADDR 0x18
155 #define CONFIG_POWER_I2C
162 #define CONFIG_ENV_OVERWRITE
165 #if defined(CONFIG_SD_BOOT)
166 #define CONFIG_SYS_MMC_ENV_DEV 0
167 #define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
168 #define CONFIG_ENV_SIZE 0x2000
170 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
171 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
172 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */
175 #define AQR105_IRQ_MASK 0x80000000
180 #define CONFIG_PHY_REALTEK
183 #ifdef CONFIG_SYS_DPAA_FMAN
184 #define CONFIG_FMAN_ENET
185 #define CONFIG_PHY_AQUANTIA
186 #define CONFIG_PHYLIB_10G
187 #define RGMII_PHY1_ADDR 0x1
188 #define RGMII_PHY2_ADDR 0x2
190 #define SGMII_PHY1_ADDR 0x3
191 #define SGMII_PHY2_ADDR 0x4
193 #define FM1_10GEC1_PHY_ADDR 0x0
195 #define FDT_SEQ_MACADDR_FROM_ENV
197 #define CONFIG_ETHPRIME "FM1@DTSEC3"
204 #ifdef CONFIG_FSL_QSPI
205 #define CONFIG_SPI_FLASH_SPANSION
206 #define FSL_QSPI_FLASH_SIZE (1 << 26)
207 #define FSL_QSPI_FLASH_NUM 2
212 #undef CONFIG_BOOTCOMMAND
213 #if defined(CONFIG_QSPI_BOOT)
214 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
215 "env exists secureboot && esbc_halt;;"
216 #elif defined(CONFIG_SD_BOOT)
217 #define CONFIG_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \
218 "env exists secureboot && esbc_halt;"
222 #include <asm/fsl_secure_boot.h>
224 #endif /* __LS1046ARDB_H__ */