Merge branch '2019-05-24-master-imports'
[platform/kernel/u-boot.git] / include / configs / ls1046ardb.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2016 Freescale Semiconductor
4  */
5
6 #ifndef __LS1046ARDB_H__
7 #define __LS1046ARDB_H__
8
9 #include "ls1046a_common.h"
10
11 #define CONFIG_SYS_CLK_FREQ             100000000
12 #define CONFIG_DDR_CLK_FREQ             100000000
13
14 #define CONFIG_LAYERSCAPE_NS_ACCESS
15
16 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
17 /* Physical Memory Map */
18 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
19
20 #define CONFIG_DDR_SPD
21 #define SPD_EEPROM_ADDRESS              0x51
22 #define CONFIG_SYS_SPD_BUS_NUM          0
23
24 #define CONFIG_DDR_ECC
25 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
26 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
27
28 #ifdef CONFIG_SD_BOOT
29 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
30 #ifdef CONFIG_EMMC_BOOT
31 #define CONFIG_SYS_FSL_PBL_RCW \
32         board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
33 #else
34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
35 #endif
36 #elif defined(CONFIG_QSPI_BOOT)
37 #define CONFIG_SYS_FSL_PBL_RCW \
38         board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg
39 #define CONFIG_SYS_FSL_PBL_PBI \
40         board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg
41 #define CONFIG_SYS_UBOOT_BASE           0x40100000
42 #define CONFIG_SYS_SPL_ARGS_ADDR        0x90000000
43 #endif
44
45 #ifndef SPL_NO_IFC
46 /* IFC */
47 #define CONFIG_FSL_IFC
48 /*
49  * NAND Flash Definitions
50  */
51 #define CONFIG_NAND_FSL_IFC
52 #endif
53
54 #define CONFIG_SYS_NAND_BASE            0x7e800000
55 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
56
57 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
58 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
59                                 | CSPR_PORT_SIZE_8      \
60                                 | CSPR_MSEL_NAND        \
61                                 | CSPR_V)
62 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
63 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
64                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
65                                 | CSOR_NAND_ECC_MODE_8  /* 8-bit ECC */ \
66                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
67                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
68                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
69                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
70
71 #define CONFIG_SYS_NAND_ONFI_DETECTION
72
73 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
74                                         FTIM0_NAND_TWP(0x18)   | \
75                                         FTIM0_NAND_TWCHT(0x7) | \
76                                         FTIM0_NAND_TWH(0xa))
77 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
78                                         FTIM1_NAND_TWBE(0x39)  | \
79                                         FTIM1_NAND_TRR(0xe)   | \
80                                         FTIM1_NAND_TRP(0x18))
81 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
82                                         FTIM2_NAND_TREH(0xa) | \
83                                         FTIM2_NAND_TWHRE(0x1e))
84 #define CONFIG_SYS_NAND_FTIM3           0x0
85
86 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
87 #define CONFIG_SYS_MAX_NAND_DEVICE      1
88 #define CONFIG_MTD_NAND_VERIFY_WRITE
89
90 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
91
92 /*
93  * CPLD
94  */
95 #define CONFIG_SYS_CPLD_BASE            0x7fb00000
96 #define CPLD_BASE_PHYS                  CONFIG_SYS_CPLD_BASE
97
98 #define CONFIG_SYS_CPLD_CSPR_EXT        (0x0)
99 #define CONFIG_SYS_CPLD_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
100                                         CSPR_PORT_SIZE_8 | \
101                                         CSPR_MSEL_GPCM | \
102                                         CSPR_V)
103 #define CONFIG_SYS_CPLD_AMASK           IFC_AMASK(64 * 1024)
104 #define CONFIG_SYS_CPLD_CSOR            CSOR_NOR_ADM_SHIFT(16)
105
106 /* CPLD Timing parameters for IFC GPCM */
107 #define CONFIG_SYS_CPLD_FTIM0           (FTIM0_GPCM_TACSE(0x0e) | \
108                                         FTIM0_GPCM_TEADC(0x0e) | \
109                                         FTIM0_GPCM_TEAHC(0x0e))
110 #define CONFIG_SYS_CPLD_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
111                                         FTIM1_GPCM_TRAD(0x3f))
112 #define CONFIG_SYS_CPLD_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
113                                         FTIM2_GPCM_TCH(0xf) | \
114                                         FTIM2_GPCM_TWP(0x3E))
115 #define CONFIG_SYS_CPLD_FTIM3           0x0
116
117 /* IFC Timing Params */
118 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
119 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
120 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
121 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
122 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
123 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
124 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
125 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
126
127 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_CPLD_CSPR_EXT
128 #define CONFIG_SYS_CSPR2                CONFIG_SYS_CPLD_CSPR
129 #define CONFIG_SYS_AMASK2               CONFIG_SYS_CPLD_AMASK
130 #define CONFIG_SYS_CSOR2                CONFIG_SYS_CPLD_CSOR
131 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_CPLD_FTIM0
132 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_CPLD_FTIM1
133 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_CPLD_FTIM2
134 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_CPLD_FTIM3
135
136 /* EEPROM */
137 #define CONFIG_ID_EEPROM
138 #define CONFIG_SYS_I2C_EEPROM_NXID
139 #define CONFIG_SYS_EEPROM_BUS_NUM               0
140 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x53
141 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
142 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
143 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
144 #define I2C_RETIMER_ADDR                        0x18
145
146 /* PMIC */
147 #define CONFIG_POWER
148 #ifdef CONFIG_POWER
149 #define CONFIG_POWER_I2C
150 #endif
151
152 /*
153  * Environment
154  */
155 #ifndef SPL_NO_ENV
156 #define CONFIG_ENV_OVERWRITE
157 #endif
158
159 #ifdef CONFIG_TFABOOT
160 #define CONFIG_SYS_MMC_ENV_DEV          0
161
162 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
163 #define CONFIG_ENV_OFFSET               0x500000        /* 5MB */
164 #define CONFIG_ENV_SECT_SIZE            0x40000         /* 256KB */
165 #else
166 #if defined(CONFIG_SD_BOOT)
167 #define CONFIG_SYS_MMC_ENV_DEV          0
168 #define CONFIG_ENV_OFFSET               (3 * 1024 * 1024)
169 #define CONFIG_ENV_SIZE                 0x2000
170 #else
171 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
172 #define CONFIG_ENV_OFFSET               0x300000        /* 3MB */
173 #define CONFIG_ENV_SECT_SIZE            0x40000         /* 256KB */
174 #endif
175 #endif
176
177 #define AQR105_IRQ_MASK                 0x80000000
178 /* FMan */
179 #ifndef SPL_NO_FMAN
180
181 #ifdef CONFIG_NET
182 #define CONFIG_PHY_REALTEK
183 #endif
184
185 #ifdef CONFIG_SYS_DPAA_FMAN
186 #define CONFIG_FMAN_ENET
187 #define RGMII_PHY1_ADDR                 0x1
188 #define RGMII_PHY2_ADDR                 0x2
189
190 #define SGMII_PHY1_ADDR                 0x3
191 #define SGMII_PHY2_ADDR                 0x4
192
193 #define FM1_10GEC1_PHY_ADDR             0x0
194
195 #define FDT_SEQ_MACADDR_FROM_ENV
196
197 #define CONFIG_ETHPRIME                 "FM1@DTSEC3"
198 #endif
199
200 #endif
201
202 /* QSPI device */
203 #ifndef SPL_NO_QSPI
204 #ifdef CONFIG_FSL_QSPI
205 #define CONFIG_SPI_FLASH_SPANSION
206 #define FSL_QSPI_FLASH_SIZE             (1 << 26)
207 #define FSL_QSPI_FLASH_NUM              2
208 #endif
209 #endif
210
211 #ifndef SPL_NO_MISC
212 #undef CONFIG_BOOTCOMMAND
213 #ifdef CONFIG_TFABOOT
214 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "   \
215                            "env exists secureboot && esbc_halt;;"
216 #define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; "    \
217                            "env exists secureboot && esbc_halt;"
218 #else
219 #if defined(CONFIG_QSPI_BOOT)
220 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "     \
221                            "env exists secureboot && esbc_halt;;"
222 #elif defined(CONFIG_SD_BOOT)
223 #define CONFIG_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; "        \
224                            "env exists secureboot && esbc_halt;"
225 #endif
226 #endif
227 #endif
228
229 #include <asm/fsl_secure_boot.h>
230
231 #endif /* __LS1046ARDB_H__ */