include/configs/ls1046ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2016 Freescale Semiconductor
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __LS1046ARDB_H__
   8 #define __LS1046ARDB_H__
   9
  10 #include "ls1046a_common.h"
  11
  12 #define CONFIG_LAYERSCAPE_NS_ACCESS
  13
  14 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  15 /* Physical Memory Map */
  16 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  17
  18 #define SPD_EEPROM_ADDRESS              0x51
  19 #define CONFIG_SYS_SPD_BUS_NUM          0
  20
  21 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  22
  23 #if defined(CONFIG_QSPI_BOOT)
  24 #define CONFIG_SYS_UBOOT_BASE           0x40100000
  25 #define CONFIG_SYS_SPL_ARGS_ADDR        0x90000000
  26 #endif
  27
  28 #define CONFIG_SYS_NAND_BASE            0x7e800000
  29 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
  30
  31 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  32 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  33                                 | CSPR_PORT_SIZE_8      \
  34                                 | CSPR_MSEL_NAND        \
  35                                 | CSPR_V)
  36 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
  37 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  38                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  39                                 | CSOR_NAND_ECC_MODE_8  /* 8-bit ECC */ \
  40                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
  41                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
  42                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
  43                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
  44
  45 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
  46                                         FTIM0_NAND_TWP(0x18)   | \
  47                                         FTIM0_NAND_TWCHT(0x7) | \
  48                                         FTIM0_NAND_TWH(0xa))
  49 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
  50                                         FTIM1_NAND_TWBE(0x39)  | \
  51                                         FTIM1_NAND_TRR(0xe)   | \
  52                                         FTIM1_NAND_TRP(0x18))
  53 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
  54                                         FTIM2_NAND_TREH(0xa) | \
  55                                         FTIM2_NAND_TWHRE(0x1e))
  56 #define CONFIG_SYS_NAND_FTIM3           0x0
  57
  58 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
  59 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  60 #define CONFIG_MTD_NAND_VERIFY_WRITE
  61
  62 /*
  63  * CPLD
  64  */
  65 #define CONFIG_SYS_CPLD_BASE            0x7fb00000
  66 #define CPLD_BASE_PHYS                  CONFIG_SYS_CPLD_BASE
  67
  68 #define CONFIG_SYS_CPLD_CSPR_EXT        (0x0)
  69 #define CONFIG_SYS_CPLD_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
  70                                         CSPR_PORT_SIZE_8 | \
  71                                         CSPR_MSEL_GPCM | \
  72                                         CSPR_V)
  73 #define CONFIG_SYS_CPLD_AMASK           IFC_AMASK(64 * 1024)
  74 #define CONFIG_SYS_CPLD_CSOR            CSOR_NOR_ADM_SHIFT(16)
  75
  76 /* CPLD Timing parameters for IFC GPCM */
  77 #define CONFIG_SYS_CPLD_FTIM0           (FTIM0_GPCM_TACSE(0x0e) | \
  78                                         FTIM0_GPCM_TEADC(0x0e) | \
  79                                         FTIM0_GPCM_TEAHC(0x0e))
  80 #define CONFIG_SYS_CPLD_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
  81                                         FTIM1_GPCM_TRAD(0x3f))
  82 #define CONFIG_SYS_CPLD_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
  83                                         FTIM2_GPCM_TCH(0xf) | \
  84                                         FTIM2_GPCM_TWP(0x3E))
  85 #define CONFIG_SYS_CPLD_FTIM3           0x0
  86
  87 /* IFC Timing Params */
  88 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
  89 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
  90 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
  91 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
  92 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
  93 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
  94 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
  95 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
  96
  97 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_CPLD_CSPR_EXT
  98 #define CONFIG_SYS_CSPR2                CONFIG_SYS_CPLD_CSPR
  99 #define CONFIG_SYS_AMASK2               CONFIG_SYS_CPLD_AMASK
 100 #define CONFIG_SYS_CSOR2                CONFIG_SYS_CPLD_CSOR
 101 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_CPLD_FTIM0
 102 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_CPLD_FTIM1
 103 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_CPLD_FTIM2
 104 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_CPLD_FTIM3
 105
 106 /* EEPROM */
 107 #define CONFIG_SYS_I2C_EEPROM_NXID
 108 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 109 #define I2C_RETIMER_ADDR                        0x18
 110
 111 /* PMIC */
 112
 113 /*
 114  * Environment
 115  */
 116 #define CONFIG_SYS_FSL_QSPI_BASE        0x40000000
 117
 118 #define AQR105_IRQ_MASK                 0x80000000
 119 /* FMan */
 120 #ifndef SPL_NO_FMAN
 121 #ifdef CONFIG_SYS_DPAA_FMAN
 122 #define RGMII_PHY1_ADDR                 0x1
 123 #define RGMII_PHY2_ADDR                 0x2
 124
 125 #define SGMII_PHY1_ADDR                 0x3
 126 #define SGMII_PHY2_ADDR                 0x4
 127
 128 #define FM1_10GEC1_PHY_ADDR             0x0
 129
 130 #define FDT_SEQ_MACADDR_FROM_ENV
 131
 132 #define CONFIG_ETHPRIME                 "FM1@DTSEC3"
 133 #endif
 134
 135 #endif
 136
 137 #ifndef SPL_NO_MISC
 138 #ifdef CONFIG_TFABOOT
 139 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "   \
 140                            "env exists secureboot && esbc_halt;;"
 141 #define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; "    \
 142                            "env exists secureboot && esbc_halt;"
 143 #endif
 144 #endif
 145
 146 #include <asm/fsl_secure_boot.h>
 147
 148 #endif /* __LS1046ARDB_H__ */