1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016 Freescale Semiconductor
7 #ifndef __LS1046ARDB_H__
8 #define __LS1046ARDB_H__
10 #include "ls1046a_common.h"
12 #define CONFIG_LAYERSCAPE_NS_ACCESS
14 /* Physical Memory Map */
16 #define SPD_EEPROM_ADDRESS 0x51
17 #define CONFIG_SYS_SPD_BUS_NUM 0
19 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
21 #if defined(CONFIG_QSPI_BOOT)
22 #define CONFIG_SYS_UBOOT_BASE 0x40100000
25 #define CONFIG_SYS_NAND_BASE 0x7e800000
26 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
28 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
29 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
33 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
34 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
35 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
36 | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
37 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
38 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
39 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
40 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
42 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
43 FTIM0_NAND_TWP(0x18) | \
44 FTIM0_NAND_TWCHT(0x7) | \
46 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
47 FTIM1_NAND_TWBE(0x39) | \
48 FTIM1_NAND_TRR(0xe) | \
50 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
51 FTIM2_NAND_TREH(0xa) | \
52 FTIM2_NAND_TWHRE(0x1e))
53 #define CONFIG_SYS_NAND_FTIM3 0x0
55 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
56 #define CONFIG_SYS_MAX_NAND_DEVICE 1
57 #define CONFIG_MTD_NAND_VERIFY_WRITE
62 #define CONFIG_SYS_CPLD_BASE 0x7fb00000
63 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
65 #define CONFIG_SYS_CPLD_CSPR_EXT (0x0)
66 #define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
70 #define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
71 #define CONFIG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16)
73 /* CPLD Timing parameters for IFC GPCM */
74 #define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
75 FTIM0_GPCM_TEADC(0x0e) | \
76 FTIM0_GPCM_TEAHC(0x0e))
77 #define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
78 FTIM1_GPCM_TRAD(0x3f))
79 #define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
80 FTIM2_GPCM_TCH(0xf) | \
82 #define CONFIG_SYS_CPLD_FTIM3 0x0
84 /* IFC Timing Params */
85 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
86 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
87 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
88 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
89 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
90 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
91 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
92 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
94 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
95 #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
96 #define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK
97 #define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR
98 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0
99 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1
100 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
101 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
104 #define CONFIG_SYS_I2C_EEPROM_NXID
105 #define CONFIG_SYS_EEPROM_BUS_NUM 0
106 #define I2C_RETIMER_ADDR 0x18
113 #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
115 #define AQR105_IRQ_MASK 0x80000000
118 #ifdef CONFIG_SYS_DPAA_FMAN
119 #define RGMII_PHY1_ADDR 0x1
120 #define RGMII_PHY2_ADDR 0x2
122 #define SGMII_PHY1_ADDR 0x3
123 #define SGMII_PHY2_ADDR 0x4
125 #define FM1_10GEC1_PHY_ADDR 0x0
127 #define FDT_SEQ_MACADDR_FROM_ENV
133 #ifdef CONFIG_TFABOOT
134 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
135 "env exists secureboot && esbc_halt;;"
136 #define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \
137 "env exists secureboot && esbc_halt;"
141 #include <asm/fsl_secure_boot.h>
143 #endif /* __LS1046ARDB_H__ */