1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016 Freescale Semiconductor
7 #ifndef __LS1046ARDB_H__
8 #define __LS1046ARDB_H__
10 #include "ls1046a_common.h"
12 /* Physical Memory Map */
14 #define SPD_EEPROM_ADDRESS 0x51
16 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
18 #if defined(CONFIG_QSPI_BOOT)
19 #define CONFIG_SYS_UBOOT_BASE 0x40100000
22 #define CONFIG_SYS_NAND_BASE 0x7e800000
23 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
25 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
26 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
30 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
31 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
32 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
33 | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
34 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
35 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
36 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
37 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
39 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
40 FTIM0_NAND_TWP(0x18) | \
41 FTIM0_NAND_TWCHT(0x7) | \
43 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
44 FTIM1_NAND_TWBE(0x39) | \
45 FTIM1_NAND_TRR(0xe) | \
47 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
48 FTIM2_NAND_TREH(0xa) | \
49 FTIM2_NAND_TWHRE(0x1e))
50 #define CONFIG_SYS_NAND_FTIM3 0x0
52 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
53 #define CONFIG_SYS_MAX_NAND_DEVICE 1
54 #define CONFIG_MTD_NAND_VERIFY_WRITE
59 #define CONFIG_SYS_CPLD_BASE 0x7fb00000
60 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
62 #define CONFIG_SYS_CPLD_CSPR_EXT (0x0)
63 #define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
67 #define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
68 #define CONFIG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16)
70 /* CPLD Timing parameters for IFC GPCM */
71 #define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
72 FTIM0_GPCM_TEADC(0x0e) | \
73 FTIM0_GPCM_TEAHC(0x0e))
74 #define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
75 FTIM1_GPCM_TRAD(0x3f))
76 #define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
77 FTIM2_GPCM_TCH(0xf) | \
79 #define CONFIG_SYS_CPLD_FTIM3 0x0
81 /* IFC Timing Params */
82 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
83 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
84 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
85 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
86 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
87 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
88 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
89 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
91 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
92 #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
93 #define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK
94 #define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR
95 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0
96 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1
97 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
98 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
101 #define CONFIG_SYS_I2C_EEPROM_NXID
102 #define CONFIG_SYS_EEPROM_BUS_NUM 0
103 #define I2C_RETIMER_ADDR 0x18
110 #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
112 #define AQR105_IRQ_MASK 0x80000000
115 #ifdef CONFIG_SYS_DPAA_FMAN
116 #define RGMII_PHY1_ADDR 0x1
117 #define RGMII_PHY2_ADDR 0x2
119 #define SGMII_PHY1_ADDR 0x3
120 #define SGMII_PHY2_ADDR 0x4
122 #define FM1_10GEC1_PHY_ADDR 0x0
124 #define FDT_SEQ_MACADDR_FROM_ENV
130 #ifdef CONFIG_TFABOOT
131 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
132 "env exists secureboot && esbc_halt;;"
133 #define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \
134 "env exists secureboot && esbc_halt;"
138 #include <asm/fsl_secure_boot.h>
140 #endif /* __LS1046ARDB_H__ */