include/configs/ls1046ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2016 Freescale Semiconductor
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __LS1046ARDB_H__
   8 #define __LS1046ARDB_H__
   9
  10 #include "ls1046a_common.h"
  11
  12 #define CONFIG_SYS_CLK_FREQ             100000000
  13 #define CONFIG_DDR_CLK_FREQ             100000000
  14
  15 #define CONFIG_LAYERSCAPE_NS_ACCESS
  16
  17 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  18 /* Physical Memory Map */
  19 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  20
  21 #define CONFIG_DDR_SPD
  22 #define SPD_EEPROM_ADDRESS              0x51
  23 #define CONFIG_SYS_SPD_BUS_NUM          0
  24
  25 #define CONFIG_DDR_ECC
  26 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  27 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  28
  29 #ifdef CONFIG_SD_BOOT
  30 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
  31 #ifdef CONFIG_EMMC_BOOT
  32 #define CONFIG_SYS_FSL_PBL_RCW \
  33         board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
  34 #else
  35 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
  36 #endif
  37 #elif defined(CONFIG_QSPI_BOOT)
  38 #define CONFIG_SYS_FSL_PBL_RCW \
  39         board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg
  40 #define CONFIG_SYS_FSL_PBL_PBI \
  41         board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg
  42 #define CONFIG_SYS_UBOOT_BASE           0x40100000
  43 #define CONFIG_SYS_SPL_ARGS_ADDR        0x90000000
  44 #endif
  45
  46 #ifndef SPL_NO_IFC
  47 /* IFC */
  48 #define CONFIG_FSL_IFC
  49 /*
  50  * NAND Flash Definitions
  51  */
  52 #define CONFIG_NAND_FSL_IFC
  53 #endif
  54
  55 #define CONFIG_SYS_NAND_BASE            0x7e800000
  56 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
  57
  58 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  59 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  60                                 | CSPR_PORT_SIZE_8      \
  61                                 | CSPR_MSEL_NAND        \
  62                                 | CSPR_V)
  63 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
  64 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  65                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  66                                 | CSOR_NAND_ECC_MODE_8  /* 8-bit ECC */ \
  67                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
  68                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
  69                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
  70                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
  71
  72 #define CONFIG_SYS_NAND_ONFI_DETECTION
  73
  74 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
  75                                         FTIM0_NAND_TWP(0x18)   | \
  76                                         FTIM0_NAND_TWCHT(0x7) | \
  77                                         FTIM0_NAND_TWH(0xa))
  78 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
  79                                         FTIM1_NAND_TWBE(0x39)  | \
  80                                         FTIM1_NAND_TRR(0xe)   | \
  81                                         FTIM1_NAND_TRP(0x18))
  82 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
  83                                         FTIM2_NAND_TREH(0xa) | \
  84                                         FTIM2_NAND_TWHRE(0x1e))
  85 #define CONFIG_SYS_NAND_FTIM3           0x0
  86
  87 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
  88 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  89 #define CONFIG_MTD_NAND_VERIFY_WRITE
  90
  91 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
  92
  93 /*
  94  * CPLD
  95  */
  96 #define CONFIG_SYS_CPLD_BASE            0x7fb00000
  97 #define CPLD_BASE_PHYS                  CONFIG_SYS_CPLD_BASE
  98
  99 #define CONFIG_SYS_CPLD_CSPR_EXT        (0x0)
 100 #define CONFIG_SYS_CPLD_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 101                                         CSPR_PORT_SIZE_8 | \
 102                                         CSPR_MSEL_GPCM | \
 103                                         CSPR_V)
 104 #define CONFIG_SYS_CPLD_AMASK           IFC_AMASK(64 * 1024)
 105 #define CONFIG_SYS_CPLD_CSOR            CSOR_NOR_ADM_SHIFT(16)
 106
 107 /* CPLD Timing parameters for IFC GPCM */
 108 #define CONFIG_SYS_CPLD_FTIM0           (FTIM0_GPCM_TACSE(0x0e) | \
 109                                         FTIM0_GPCM_TEADC(0x0e) | \
 110                                         FTIM0_GPCM_TEAHC(0x0e))
 111 #define CONFIG_SYS_CPLD_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
 112                                         FTIM1_GPCM_TRAD(0x3f))
 113 #define CONFIG_SYS_CPLD_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
 114                                         FTIM2_GPCM_TCH(0xf) | \
 115                                         FTIM2_GPCM_TWP(0x3E))
 116 #define CONFIG_SYS_CPLD_FTIM3           0x0
 117
 118 /* IFC Timing Params */
 119 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 120 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 121 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 122 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 123 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 124 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 125 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 126 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 127
 128 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_CPLD_CSPR_EXT
 129 #define CONFIG_SYS_CSPR2                CONFIG_SYS_CPLD_CSPR
 130 #define CONFIG_SYS_AMASK2               CONFIG_SYS_CPLD_AMASK
 131 #define CONFIG_SYS_CSOR2                CONFIG_SYS_CPLD_CSOR
 132 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_CPLD_FTIM0
 133 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_CPLD_FTIM1
 134 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_CPLD_FTIM2
 135 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_CPLD_FTIM3
 136
 137 /* EEPROM */
 138 #define CONFIG_ID_EEPROM
 139 #define CONFIG_SYS_I2C_EEPROM_NXID
 140 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 141 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x53
 142 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 143 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 144 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 145 #define I2C_RETIMER_ADDR                        0x18
 146
 147 /* PMIC */
 148 #define CONFIG_POWER
 149 #ifdef CONFIG_POWER
 150 #define CONFIG_POWER_I2C
 151 #endif
 152
 153 /*
 154  * Environment
 155  */
 156 #ifndef SPL_NO_ENV
 157 #define CONFIG_ENV_OVERWRITE
 158 #endif
 159
 160 #ifdef CONFIG_TFABOOT
 161 #define CONFIG_SYS_MMC_ENV_DEV          0
 162
 163 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 164 #define CONFIG_ENV_OFFSET               0x500000        /* 5MB */
 165 #define CONFIG_ENV_SECT_SIZE            0x40000         /* 256KB */
 166 #define CONFIG_SYS_FSL_QSPI_BASE        0x40000000
 167 #define CONFIG_ENV_ADDR CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET
 168 #else
 169 #if defined(CONFIG_SD_BOOT)
 170 #define CONFIG_SYS_MMC_ENV_DEV          0
 171 #define CONFIG_ENV_OFFSET               (3 * 1024 * 1024)
 172 #define CONFIG_ENV_SIZE                 0x2000
 173 #else
 174 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 175 #define CONFIG_ENV_OFFSET               0x300000        /* 3MB */
 176 #define CONFIG_ENV_SECT_SIZE            0x40000         /* 256KB */
 177 #endif
 178 #endif
 179
 180 #define AQR105_IRQ_MASK                 0x80000000
 181 /* FMan */
 182 #ifndef SPL_NO_FMAN
 183
 184 #ifdef CONFIG_NET
 185 #define CONFIG_PHY_REALTEK
 186 #endif
 187
 188 #ifdef CONFIG_SYS_DPAA_FMAN
 189 #define RGMII_PHY1_ADDR                 0x1
 190 #define RGMII_PHY2_ADDR                 0x2
 191
 192 #define SGMII_PHY1_ADDR                 0x3
 193 #define SGMII_PHY2_ADDR                 0x4
 194
 195 #define FM1_10GEC1_PHY_ADDR             0x0
 196
 197 #define FDT_SEQ_MACADDR_FROM_ENV
 198
 199 #define CONFIG_ETHPRIME                 "FM1@DTSEC3"
 200 #endif
 201
 202 #endif
 203
 204 /* QSPI device */
 205 #ifndef SPL_NO_QSPI
 206 #ifdef CONFIG_FSL_QSPI
 207 #define CONFIG_SPI_FLASH_SPANSION
 208 #define FSL_QSPI_FLASH_SIZE             (1 << 26)
 209 #define FSL_QSPI_FLASH_NUM              2
 210 #endif
 211 #endif
 212
 213 #ifndef SPL_NO_MISC
 214 #undef CONFIG_BOOTCOMMAND
 215 #ifdef CONFIG_TFABOOT
 216 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "   \
 217                            "env exists secureboot && esbc_halt;;"
 218 #define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; "    \
 219                            "env exists secureboot && esbc_halt;"
 220 #else
 221 #if defined(CONFIG_QSPI_BOOT)
 222 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "     \
 223                            "env exists secureboot && esbc_halt;;"
 224 #elif defined(CONFIG_SD_BOOT)
 225 #define CONFIG_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; "        \
 226                            "env exists secureboot && esbc_halt;"
 227 #endif
 228 #endif
 229 #endif
 230
 231 #include <asm/fsl_secure_boot.h>
 232
 233 #endif /* __LS1046ARDB_H__ */