Merge tag 'efi-2022-04-rc1-2' of https://source.denx.de/u-boot/custodians/u-boot-efi
[platform/kernel/u-boot.git] / include / configs / ls1046aqds.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2016 Freescale Semiconductor, Inc.
4  */
5
6 #ifndef __LS1046AQDS_H__
7 #define __LS1046AQDS_H__
8
9 #include "ls1046a_common.h"
10
11 #define CONFIG_LAYERSCAPE_NS_ACCESS
12
13 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
14 /* Physical Memory Map */
15 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
16
17 #define SPD_EEPROM_ADDRESS              0x51
18 #define CONFIG_SYS_SPD_BUS_NUM          0
19
20 #ifdef CONFIG_DDR_ECC
21 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
22 #endif
23
24 #ifdef CONFIG_SYS_DPAA_FMAN
25 #define RGMII_PHY1_ADDR         0x1
26 #define RGMII_PHY2_ADDR         0x2
27 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
28 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
29 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
30 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
31 /* PHY address on QSGMII riser card on slot 2 */
32 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
33 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
34 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
35 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
36 #endif
37
38 /* IFC */
39 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
40 /*
41  * CONFIG_SYS_FLASH_BASE has the final address (core view)
42  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
43  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
44  * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
45  */
46 #define CONFIG_SYS_FLASH_BASE                   0x60000000
47 #define CONFIG_SYS_FLASH_BASE_PHYS              CONFIG_SYS_FLASH_BASE
48 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY        0x00000000
49
50 #ifdef CONFIG_MTD_NOR_FLASH
51 #define CONFIG_SYS_FLASH_QUIET_TEST
52 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
53 #endif
54 #endif
55
56 /* LPUART */
57 #ifdef CONFIG_LPUART
58 #define CONFIG_LPUART_32B_REG
59 #define CFG_UART_MUX_MASK       0x6
60 #define CFG_UART_MUX_SHIFT      1
61 #define CFG_LPUART_EN           0x2
62 #endif
63
64 /* EEPROM */
65 #define CONFIG_SYS_I2C_EEPROM_NXID
66 #define CONFIG_SYS_EEPROM_BUS_NUM               0
67
68 /*
69  * IFC Definitions
70  */
71 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
72 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
73 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
74                                 CSPR_PORT_SIZE_16 | \
75                                 CSPR_MSEL_NOR | \
76                                 CSPR_V)
77 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
78 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
79                                 + 0x8000000) | \
80                                 CSPR_PORT_SIZE_16 | \
81                                 CSPR_MSEL_NOR | \
82                                 CSPR_V)
83 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
84
85 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
86                                         CSOR_NOR_TRHZ_80)
87 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
88                                         FTIM0_NOR_TEADC(0x5) | \
89                                         FTIM0_NOR_TAVDS(0x6) | \
90                                         FTIM0_NOR_TEAHC(0x5))
91 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
92                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
93                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
94 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x8) | \
95                                         FTIM2_NOR_TCH(0x8) | \
96                                         FTIM2_NOR_TWPH(0xe) | \
97                                         FTIM2_NOR_TWP(0x1c))
98 #define CONFIG_SYS_NOR_FTIM3            0
99
100 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
101 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
102 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
103
104 #define CONFIG_SYS_FLASH_EMPTY_INFO
105 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
106                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
107
108 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
109 #define CONFIG_SYS_WRITE_SWAPPED_DATA
110
111 /*
112  * NAND Flash Definitions
113  */
114
115 #define CONFIG_SYS_NAND_BASE            0x7e800000
116 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
117
118 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
119
120 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
121                                 | CSPR_PORT_SIZE_8      \
122                                 | CSPR_MSEL_NAND        \
123                                 | CSPR_V)
124 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
125 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
126                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
127                                 | CSOR_NAND_ECC_MODE_8  /* 8-bit ECC */ \
128                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
129                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
130                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
131                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
132
133 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
134                                         FTIM0_NAND_TWP(0x18)   | \
135                                         FTIM0_NAND_TWCHT(0x7) | \
136                                         FTIM0_NAND_TWH(0xa))
137 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
138                                         FTIM1_NAND_TWBE(0x39)  | \
139                                         FTIM1_NAND_TRR(0xe)   | \
140                                         FTIM1_NAND_TRP(0x18))
141 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
142                                         FTIM2_NAND_TREH(0xa) | \
143                                         FTIM2_NAND_TWHRE(0x1e))
144 #define CONFIG_SYS_NAND_FTIM3           0x0
145
146 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
147 #define CONFIG_SYS_MAX_NAND_DEVICE      1
148 #define CONFIG_MTD_NAND_VERIFY_WRITE
149 #endif
150
151 #ifdef CONFIG_NAND_BOOT
152 #define CONFIG_SPL_PAD_TO               0x40000         /* block aligned */
153 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
154 #endif
155
156 #if defined(CONFIG_TFABOOT) || \
157         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
158 #define CONFIG_QIXIS_I2C_ACCESS
159 #endif
160
161 /*
162  * QIXIS Definitions
163  */
164 #define CONFIG_FSL_QIXIS
165
166 #ifdef CONFIG_FSL_QIXIS
167 #define QIXIS_BASE                      0x7fb00000
168 #define QIXIS_BASE_PHYS                 QIXIS_BASE
169 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
170 #define QIXIS_LBMAP_SWITCH              6
171 #define QIXIS_LBMAP_MASK                0x0f
172 #define QIXIS_LBMAP_SHIFT               0
173 #define QIXIS_LBMAP_DFLTBANK            0x00
174 #define QIXIS_LBMAP_ALTBANK             0x04
175 #define QIXIS_LBMAP_NAND                0x09
176 #define QIXIS_LBMAP_SD                  0x00
177 #define QIXIS_LBMAP_SD_QSPI             0xff
178 #define QIXIS_LBMAP_QSPI                0xff
179 #define QIXIS_RCW_SRC_NAND              0x110
180 #define QIXIS_RCW_SRC_SD                0x040
181 #define QIXIS_RCW_SRC_QSPI              0x045
182 #define QIXIS_RST_CTL_RESET             0x41
183 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
184 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
185 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
186
187 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
188 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
189                                         CSPR_PORT_SIZE_8 | \
190                                         CSPR_MSEL_GPCM | \
191                                         CSPR_V)
192 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
193 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
194                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
195                                         CSOR_NOR_TRHZ_80)
196
197 /*
198  * QIXIS Timing parameters for IFC GPCM
199  */
200 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xc) | \
201                                         FTIM0_GPCM_TEADC(0x20) | \
202                                         FTIM0_GPCM_TEAHC(0x10))
203 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0x50) | \
204                                         FTIM1_GPCM_TRAD(0x1f))
205 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0x8) | \
206                                         FTIM2_GPCM_TCH(0x8) | \
207                                         FTIM2_GPCM_TWP(0xf0))
208 #define CONFIG_SYS_FPGA_FTIM3           0x0
209 #endif
210
211 #ifdef CONFIG_TFABOOT
212 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
213 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
214 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
215 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
216 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
217 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
218 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
219 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
220 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
221 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
222 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
223 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
224 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
225 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
226 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
227 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
228 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
229 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
230 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
231 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
232 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
233 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
234 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
235 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
236 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
237 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
238 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
239 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
240 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
241 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
242 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
243 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
244 #else
245 #ifdef CONFIG_NAND_BOOT
246 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
247 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
248 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
249 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
250 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
251 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
252 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
253 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
254 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
255 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
256 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
257 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
258 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
259 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
260 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
261 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
262 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
263 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
264 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
265 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
266 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
267 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
268 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
269 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
270 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
271 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
272 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
273 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
274 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
275 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
276 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
277 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
278 #else
279 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
280 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
281 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
282 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
283 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
284 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
285 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
286 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
287 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
288 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
289 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
290 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
291 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
292 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
293 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
294 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
295 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
296 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
297 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
298 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
299 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
300 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
301 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
302 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
303 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
304 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
305 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
306 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
307 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
308 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
309 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
310 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
311 #endif
312 #endif
313
314 /*
315  * I2C bus multiplexer
316  */
317 #define I2C_MUX_PCA_ADDR_PRI            0x77
318 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
319 #define I2C_RETIMER_ADDR                0x18
320 #define I2C_MUX_CH_DEFAULT              0x8
321 #define I2C_MUX_CH_CH7301               0xC
322 #define I2C_MUX_CH5                     0xD
323 #define I2C_MUX_CH6                     0xE
324 #define I2C_MUX_CH7                     0xF
325
326 #define I2C_MUX_CH_VOL_MONITOR 0xa
327
328 /* Voltage monitor on channel 2*/
329 #define I2C_VOL_MONITOR_ADDR           0x40
330 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
331 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
332 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
333
334 /* The lowest and highest voltage allowed for LS1046AQDS */
335 #define VDD_MV_MIN                      819
336 #define VDD_MV_MAX                      1212
337
338 /*
339  * Miscellaneous configurable options
340  */
341
342 #define CONFIG_SYS_INIT_SP_OFFSET \
343         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
344
345 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
346
347 /*
348  * Environment
349  */
350
351 #ifdef CONFIG_TFABOOT
352 #define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; "   \
353                            "env exists secureboot && esbc_halt;;"
354 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd"      \
355                            "env exists secureboot && esbc_halt;;"
356 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "     \
357                            "env exists secureboot && esbc_halt;;"
358 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "   \
359                            "env exists secureboot && esbc_halt;;"
360 #endif
361
362 #include <asm/fsl_secure_boot.h>
363
364 #endif /* __LS1046AQDS_H__ */