include/configs/ls1046aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __LS1046AQDS_H__
   7 #define __LS1046AQDS_H__
   8
   9 #include "ls1046a_common.h"
  10
  11 #ifndef __ASSEMBLY__
  12 unsigned long get_board_sys_clk(void);
  13 #endif
  14
  15 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  16
  17 #define CONFIG_LAYERSCAPE_NS_ACCESS
  18
  19 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  20 /* Physical Memory Map */
  21 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  22
  23 #define SPD_EEPROM_ADDRESS              0x51
  24 #define CONFIG_SYS_SPD_BUS_NUM          0
  25
  26 #ifdef CONFIG_DDR_ECC
  27 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  28 #endif
  29
  30 #ifdef CONFIG_SYS_DPAA_FMAN
  31 #define RGMII_PHY1_ADDR         0x1
  32 #define RGMII_PHY2_ADDR         0x2
  33 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  34 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  35 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  36 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  37 /* PHY address on QSGMII riser card on slot 2 */
  38 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
  39 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
  40 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
  41 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
  42 #endif
  43
  44 /* IFC */
  45 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  46 /*
  47  * CONFIG_SYS_FLASH_BASE has the final address (core view)
  48  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
  49  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  50  * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
  51  */
  52 #define CONFIG_SYS_FLASH_BASE                   0x60000000
  53 #define CONFIG_SYS_FLASH_BASE_PHYS              CONFIG_SYS_FLASH_BASE
  54 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY        0x00000000
  55
  56 #ifdef CONFIG_MTD_NOR_FLASH
  57 #define CONFIG_SYS_FLASH_QUIET_TEST
  58 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
  59 #endif
  60 #endif
  61
  62 /* LPUART */
  63 #ifdef CONFIG_LPUART
  64 #define CONFIG_LPUART_32B_REG
  65 #define CFG_UART_MUX_MASK       0x6
  66 #define CFG_UART_MUX_SHIFT      1
  67 #define CFG_LPUART_EN           0x2
  68 #endif
  69
  70 /* EEPROM */
  71 #define CONFIG_SYS_I2C_EEPROM_NXID
  72 #define CONFIG_SYS_EEPROM_BUS_NUM               0
  73
  74 /*
  75  * IFC Definitions
  76  */
  77 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  78 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  79 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  80                                 CSPR_PORT_SIZE_16 | \
  81                                 CSPR_MSEL_NOR | \
  82                                 CSPR_V)
  83 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
  84 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  85                                 + 0x8000000) | \
  86                                 CSPR_PORT_SIZE_16 | \
  87                                 CSPR_MSEL_NOR | \
  88                                 CSPR_V)
  89 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  90
  91 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  92                                         CSOR_NOR_TRHZ_80)
  93 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
  94                                         FTIM0_NOR_TEADC(0x5) | \
  95                                         FTIM0_NOR_TAVDS(0x6) | \
  96                                         FTIM0_NOR_TEAHC(0x5))
  97 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
  98                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
  99                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 100 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x8) | \
 101                                         FTIM2_NOR_TCH(0x8) | \
 102                                         FTIM2_NOR_TWPH(0xe) | \
 103                                         FTIM2_NOR_TWP(0x1c))
 104 #define CONFIG_SYS_NOR_FTIM3            0
 105
 106 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 107 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 108 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 109 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 110
 111 #define CONFIG_SYS_FLASH_EMPTY_INFO
 112 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 113                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 114
 115 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 116 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 117
 118 /*
 119  * NAND Flash Definitions
 120  */
 121
 122 #define CONFIG_SYS_NAND_BASE            0x7e800000
 123 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 124
 125 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 126
 127 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 128                                 | CSPR_PORT_SIZE_8      \
 129                                 | CSPR_MSEL_NAND        \
 130                                 | CSPR_V)
 131 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 132 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 133                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 134                                 | CSOR_NAND_ECC_MODE_8  /* 8-bit ECC */ \
 135                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 136                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 137                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 138                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 139
 140 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 141                                         FTIM0_NAND_TWP(0x18)   | \
 142                                         FTIM0_NAND_TWCHT(0x7) | \
 143                                         FTIM0_NAND_TWH(0xa))
 144 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 145                                         FTIM1_NAND_TWBE(0x39)  | \
 146                                         FTIM1_NAND_TRR(0xe)   | \
 147                                         FTIM1_NAND_TRP(0x18))
 148 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 149                                         FTIM2_NAND_TREH(0xa) | \
 150                                         FTIM2_NAND_TWHRE(0x1e))
 151 #define CONFIG_SYS_NAND_FTIM3           0x0
 152
 153 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 154 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 155 #define CONFIG_MTD_NAND_VERIFY_WRITE
 156 #endif
 157
 158 #ifdef CONFIG_NAND_BOOT
 159 #define CONFIG_SPL_PAD_TO               0x40000         /* block aligned */
 160 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
 161 #endif
 162
 163 #if defined(CONFIG_TFABOOT) || \
 164         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 165 #define CONFIG_QIXIS_I2C_ACCESS
 166 #endif
 167
 168 /*
 169  * QIXIS Definitions
 170  */
 171 #define CONFIG_FSL_QIXIS
 172
 173 #ifdef CONFIG_FSL_QIXIS
 174 #define QIXIS_BASE                      0x7fb00000
 175 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 176 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 177 #define QIXIS_LBMAP_SWITCH              6
 178 #define QIXIS_LBMAP_MASK                0x0f
 179 #define QIXIS_LBMAP_SHIFT               0
 180 #define QIXIS_LBMAP_DFLTBANK            0x00
 181 #define QIXIS_LBMAP_ALTBANK             0x04
 182 #define QIXIS_LBMAP_NAND                0x09
 183 #define QIXIS_LBMAP_SD                  0x00
 184 #define QIXIS_LBMAP_SD_QSPI             0xff
 185 #define QIXIS_LBMAP_QSPI                0xff
 186 #define QIXIS_RCW_SRC_NAND              0x110
 187 #define QIXIS_RCW_SRC_SD                0x040
 188 #define QIXIS_RCW_SRC_QSPI              0x045
 189 #define QIXIS_RST_CTL_RESET             0x41
 190 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 191 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 192 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 193
 194 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 195 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 196                                         CSPR_PORT_SIZE_8 | \
 197                                         CSPR_MSEL_GPCM | \
 198                                         CSPR_V)
 199 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 200 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 201                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 202                                         CSOR_NOR_TRHZ_80)
 203
 204 /*
 205  * QIXIS Timing parameters for IFC GPCM
 206  */
 207 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xc) | \
 208                                         FTIM0_GPCM_TEADC(0x20) | \
 209                                         FTIM0_GPCM_TEAHC(0x10))
 210 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0x50) | \
 211                                         FTIM1_GPCM_TRAD(0x1f))
 212 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0x8) | \
 213                                         FTIM2_GPCM_TCH(0x8) | \
 214                                         FTIM2_GPCM_TWP(0xf0))
 215 #define CONFIG_SYS_FPGA_FTIM3           0x0
 216 #endif
 217
 218 #ifdef CONFIG_TFABOOT
 219 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 220 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 221 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 222 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 223 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 224 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 225 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 226 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 227 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 228 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 229 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 230 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 231 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 232 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 233 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 234 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 235 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 236 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 237 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 238 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 239 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 240 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 241 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 242 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 243 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 244 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 245 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 246 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 247 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 248 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 249 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 250 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 251 #else
 252 #ifdef CONFIG_NAND_BOOT
 253 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 254 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 255 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 256 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 257 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 258 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 259 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 260 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 261 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 262 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 263 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 264 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 265 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 266 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 267 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 268 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 269 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 270 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 271 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 272 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 273 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 274 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 275 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 276 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 277 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 278 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 279 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 280 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 281 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 282 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 283 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 284 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 285 #else
 286 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 287 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 288 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 289 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 290 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 291 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 292 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 293 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 294 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 295 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 296 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 297 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 298 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 299 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 300 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 301 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 302 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 303 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 304 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 305 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 306 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 307 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 308 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 309 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 310 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 311 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 312 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 313 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 314 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 315 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 316 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 317 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 318 #endif
 319 #endif
 320
 321 /*
 322  * I2C bus multiplexer
 323  */
 324 #define I2C_MUX_PCA_ADDR_PRI            0x77
 325 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 326 #define I2C_RETIMER_ADDR                0x18
 327 #define I2C_MUX_CH_DEFAULT              0x8
 328 #define I2C_MUX_CH_CH7301               0xC
 329 #define I2C_MUX_CH5                     0xD
 330 #define I2C_MUX_CH6                     0xE
 331 #define I2C_MUX_CH7                     0xF
 332
 333 #define I2C_MUX_CH_VOL_MONITOR 0xa
 334
 335 /* Voltage monitor on channel 2*/
 336 #define I2C_VOL_MONITOR_ADDR           0x40
 337 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 338 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 339 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 340
 341 /* The lowest and highest voltage allowed for LS1046AQDS */
 342 #define VDD_MV_MIN                      819
 343 #define VDD_MV_MAX                      1212
 344
 345 /*
 346  * Miscellaneous configurable options
 347  */
 348
 349 #define CONFIG_SYS_INIT_SP_OFFSET \
 350         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 351
 352 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 353
 354 /*
 355  * Environment
 356  */
 357
 358 #ifdef CONFIG_TFABOOT
 359 #define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; "   \
 360                            "env exists secureboot && esbc_halt;;"
 361 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd"      \
 362                            "env exists secureboot && esbc_halt;;"
 363 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "     \
 364                            "env exists secureboot && esbc_halt;;"
 365 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "   \
 366                            "env exists secureboot && esbc_halt;;"
 367 #endif
 368
 369 #include <asm/fsl_secure_boot.h>
 370
 371 #endif /* __LS1046AQDS_H__ */