1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016 Freescale Semiconductor, Inc.
6 #ifndef __LS1046AQDS_H__
7 #define __LS1046AQDS_H__
9 #include "ls1046a_common.h"
12 unsigned long get_board_sys_clk(void);
13 unsigned long get_board_ddr_clk(void);
16 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
17 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
19 #define CONFIG_SKIP_LOWLEVEL_INIT
21 #define CONFIG_LAYERSCAPE_NS_ACCESS
23 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
24 /* Physical Memory Map */
25 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
27 #define CONFIG_DDR_SPD
28 #define SPD_EEPROM_ADDRESS 0x51
29 #define CONFIG_SYS_SPD_BUS_NUM 0
31 #define CONFIG_DDR_ECC
33 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
34 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
38 #ifdef CONFIG_FSL_DSPI
39 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */
40 #define CONFIG_SPI_FLASH_SST /* cs1 */
41 #define CONFIG_SPI_FLASH_EON /* cs2 */
45 #if defined(CONFIG_TFABOOT) || \
46 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
47 #ifdef CONFIG_FSL_QSPI
48 #define CONFIG_SPI_FLASH_SPANSION
52 #ifdef CONFIG_SYS_DPAA_FMAN
53 #define RGMII_PHY1_ADDR 0x1
54 #define RGMII_PHY2_ADDR 0x2
55 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
56 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
57 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
58 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
59 /* PHY address on QSGMII riser card on slot 2 */
60 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
61 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
62 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
63 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
66 #ifdef CONFIG_RAMBOOT_PBL
67 #define CONFIG_SYS_FSL_PBL_PBI \
68 board/freescale/ls1046aqds/ls1046aqds_pbi.cfg
71 #ifdef CONFIG_NAND_BOOT
72 #define CONFIG_SYS_FSL_PBL_RCW \
73 board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg
77 #ifdef CONFIG_SD_BOOT_QSPI
78 #define CONFIG_SYS_FSL_PBL_RCW \
79 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg
81 #define CONFIG_SYS_FSL_PBL_RCW \
82 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg
87 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
88 #define CONFIG_FSL_IFC
90 * CONFIG_SYS_FLASH_BASE has the final address (core view)
91 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
92 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
93 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
95 #define CONFIG_SYS_FLASH_BASE 0x60000000
96 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
97 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
99 #ifdef CONFIG_MTD_NOR_FLASH
100 #define CONFIG_SYS_FLASH_QUIET_TEST
101 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
107 #define CONFIG_LPUART_32B_REG
108 #define CFG_UART_MUX_MASK 0x6
109 #define CFG_UART_MUX_SHIFT 1
110 #define CFG_LPUART_EN 0x2
114 #define CONFIG_ID_EEPROM
115 #define CONFIG_SYS_I2C_EEPROM_NXID
116 #define CONFIG_SYS_EEPROM_BUS_NUM 0
117 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
118 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
119 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
120 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
125 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
126 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
127 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
128 CSPR_PORT_SIZE_16 | \
131 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
132 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
134 CSPR_PORT_SIZE_16 | \
137 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
139 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
141 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
142 FTIM0_NOR_TEADC(0x5) | \
143 FTIM0_NOR_TAVDS(0x6) | \
144 FTIM0_NOR_TEAHC(0x5))
145 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
146 FTIM1_NOR_TRAD_NOR(0x1a) | \
147 FTIM1_NOR_TSEQRAD_NOR(0x13))
148 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \
149 FTIM2_NOR_TCH(0x8) | \
150 FTIM2_NOR_TWPH(0xe) | \
152 #define CONFIG_SYS_NOR_FTIM3 0
154 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
155 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
156 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
157 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
159 #define CONFIG_SYS_FLASH_EMPTY_INFO
160 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
161 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
163 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
164 #define CONFIG_SYS_WRITE_SWAPPED_DATA
167 * NAND Flash Definitions
169 #define CONFIG_NAND_FSL_IFC
171 #define CONFIG_SYS_NAND_BASE 0x7e800000
172 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
174 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
176 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
180 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
181 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
182 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
183 | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
184 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
185 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
186 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
187 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
189 #define CONFIG_SYS_NAND_ONFI_DETECTION
191 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
192 FTIM0_NAND_TWP(0x18) | \
193 FTIM0_NAND_TWCHT(0x7) | \
195 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
196 FTIM1_NAND_TWBE(0x39) | \
197 FTIM1_NAND_TRR(0xe) | \
198 FTIM1_NAND_TRP(0x18))
199 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
200 FTIM2_NAND_TREH(0xa) | \
201 FTIM2_NAND_TWHRE(0x1e))
202 #define CONFIG_SYS_NAND_FTIM3 0x0
204 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
205 #define CONFIG_SYS_MAX_NAND_DEVICE 1
206 #define CONFIG_MTD_NAND_VERIFY_WRITE
208 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
211 #ifdef CONFIG_NAND_BOOT
212 #define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */
213 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
214 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
217 #if defined(CONFIG_TFABOOT) || \
218 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
219 #define CONFIG_QIXIS_I2C_ACCESS
220 #define CONFIG_SYS_I2C_EARLY_INIT
226 #define CONFIG_FSL_QIXIS
228 #ifdef CONFIG_FSL_QIXIS
229 #define QIXIS_BASE 0x7fb00000
230 #define QIXIS_BASE_PHYS QIXIS_BASE
231 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
232 #define QIXIS_LBMAP_SWITCH 6
233 #define QIXIS_LBMAP_MASK 0x0f
234 #define QIXIS_LBMAP_SHIFT 0
235 #define QIXIS_LBMAP_DFLTBANK 0x00
236 #define QIXIS_LBMAP_ALTBANK 0x04
237 #define QIXIS_LBMAP_NAND 0x09
238 #define QIXIS_LBMAP_SD 0x00
239 #define QIXIS_LBMAP_SD_QSPI 0xff
240 #define QIXIS_LBMAP_QSPI 0xff
241 #define QIXIS_RCW_SRC_NAND 0x110
242 #define QIXIS_RCW_SRC_SD 0x040
243 #define QIXIS_RCW_SRC_QSPI 0x045
244 #define QIXIS_RST_CTL_RESET 0x41
245 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
246 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
247 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
249 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
250 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
254 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
255 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
256 CSOR_NOR_NOR_MODE_AVD_NOR | \
260 * QIXIS Timing parameters for IFC GPCM
262 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
263 FTIM0_GPCM_TEADC(0x20) | \
264 FTIM0_GPCM_TEAHC(0x10))
265 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
266 FTIM1_GPCM_TRAD(0x1f))
267 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
268 FTIM2_GPCM_TCH(0x8) | \
269 FTIM2_GPCM_TWP(0xf0))
270 #define CONFIG_SYS_FPGA_FTIM3 0x0
273 #ifdef CONFIG_TFABOOT
274 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
275 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
276 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
277 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
278 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
279 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
280 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
281 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
282 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
283 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
284 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
285 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
286 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
287 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
288 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
289 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
290 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
291 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
292 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
293 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
294 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
295 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
296 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
297 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
298 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
299 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
300 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
301 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
302 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
303 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
304 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
305 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
307 #ifdef CONFIG_NAND_BOOT
308 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
309 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
310 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
311 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
312 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
313 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
314 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
315 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
316 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
317 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
318 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
319 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
320 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
321 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
322 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
323 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
324 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
325 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
326 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
327 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
328 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
329 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
330 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
331 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
332 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
333 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
334 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
335 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
336 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
337 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
338 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
339 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
341 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
342 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
343 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
344 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
345 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
346 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
347 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
348 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
349 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
350 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
351 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
352 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
353 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
354 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
355 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
356 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
357 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
358 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
359 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
360 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
361 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
362 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
363 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
364 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
365 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
366 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
367 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
368 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
369 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
370 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
371 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
372 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
377 * I2C bus multiplexer
379 #define I2C_MUX_PCA_ADDR_PRI 0x77
380 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
381 #define I2C_RETIMER_ADDR 0x18
382 #define I2C_MUX_CH_DEFAULT 0x8
383 #define I2C_MUX_CH_CH7301 0xC
384 #define I2C_MUX_CH5 0xD
385 #define I2C_MUX_CH6 0xE
386 #define I2C_MUX_CH7 0xF
388 #define I2C_MUX_CH_VOL_MONITOR 0xa
390 /* Voltage monitor on channel 2*/
391 #define I2C_VOL_MONITOR_ADDR 0x40
392 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
393 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
394 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
396 #define CONFIG_VID_FLS_ENV "ls1046aqds_vdd_mv"
397 #ifndef CONFIG_SPL_BUILD
400 #define CONFIG_VOL_MONITOR_IR36021_SET
401 #define CONFIG_VOL_MONITOR_INA220
402 /* The lowest and highest voltage allowed for LS1046AQDS */
403 #define VDD_MV_MIN 819
404 #define VDD_MV_MAX 1212
407 * Miscellaneous configurable options
410 #define CONFIG_SYS_HZ 1000
412 #define CONFIG_SYS_INIT_SP_OFFSET \
413 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
415 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
420 #define CONFIG_SYS_MMC_ENV_DEV 0
422 #define CONFIG_CMDLINE_TAG
424 #undef CONFIG_BOOTCOMMAND
425 #ifdef CONFIG_TFABOOT
426 #define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \
427 "env exists secureboot && esbc_halt;;"
428 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd" \
429 "env exists secureboot && esbc_halt;;"
430 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
431 "env exists secureboot && esbc_halt;;"
432 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
433 "env exists secureboot && esbc_halt;;"
435 #if defined(CONFIG_QSPI_BOOT)
436 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
437 "env exists secureboot && esbc_halt;;"
438 #elif defined(CONFIG_NAND_BOOT)
439 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \
440 "env exists secureboot && esbc_halt;;"
441 #elif defined(CONFIG_SD_BOOT)
442 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
443 "env exists secureboot && esbc_halt;;"
445 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
446 "env exists secureboot && esbc_halt;;"
450 #include <asm/fsl_secure_boot.h>
452 #endif /* __LS1046AQDS_H__ */