Merge git://git.denx.de/u-boot-fsl-qoriq
[platform/kernel/u-boot.git] / include / configs / ls1046aqds.h
1 /*
2  * Copyright 2016 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #ifndef __LS1046AQDS_H__
8 #define __LS1046AQDS_H__
9
10 #include "ls1046a_common.h"
11
12 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
13 #define CONFIG_SYS_TEXT_BASE            0x82000000
14 #elif defined(CONFIG_QSPI_BOOT)
15 #define CONFIG_SYS_TEXT_BASE            0x40100000
16 #else
17 #define CONFIG_SYS_TEXT_BASE            0x60100000
18 #endif
19
20 #ifndef __ASSEMBLY__
21 unsigned long get_board_sys_clk(void);
22 unsigned long get_board_ddr_clk(void);
23 #endif
24
25 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
26 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
27
28 #define CONFIG_SKIP_LOWLEVEL_INIT
29
30 #define CONFIG_LAYERSCAPE_NS_ACCESS
31
32 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
33 /* Physical Memory Map */
34 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
35 #define CONFIG_NR_DRAM_BANKS            2
36
37 #define CONFIG_DDR_SPD
38 #define SPD_EEPROM_ADDRESS              0x51
39 #define CONFIG_SYS_SPD_BUS_NUM          0
40
41 #ifndef CONFIG_SPL
42 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
43 #endif
44
45 #define CONFIG_DDR_ECC
46 #ifdef CONFIG_DDR_ECC
47 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
48 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
49 #endif
50
51 /* DSPI */
52 #ifdef CONFIG_FSL_DSPI
53 #define CONFIG_SPI_FLASH_STMICRO        /* cs0 */
54 #define CONFIG_SPI_FLASH_SST            /* cs1 */
55 #define CONFIG_SPI_FLASH_EON            /* cs2 */
56 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
57 #define CONFIG_SF_DEFAULT_BUS           1
58 #define CONFIG_SF_DEFAULT_CS            0
59 #endif
60 #endif
61
62 /* QSPI */
63 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
64 #ifdef CONFIG_FSL_QSPI
65 #define CONFIG_SPI_FLASH_SPANSION
66 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
67 #define FSL_QSPI_FLASH_NUM              2
68 #endif
69 #endif
70
71 #ifdef CONFIG_SYS_DPAA_FMAN
72 #define CONFIG_FMAN_ENET
73 #define CONFIG_PHY_VITESSE
74 #define CONFIG_PHY_REALTEK
75 #define CONFIG_PHYLIB_10G
76 #define RGMII_PHY1_ADDR         0x1
77 #define RGMII_PHY2_ADDR         0x2
78 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
79 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
80 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
81 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
82 /* PHY address on QSGMII riser card on slot 2 */
83 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
84 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
85 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
86 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
87 #endif
88
89 #ifdef CONFIG_RAMBOOT_PBL
90 #define CONFIG_SYS_FSL_PBL_PBI \
91         board/freescale/ls1046aqds/ls1046aqds_pbi.cfg
92 #endif
93
94 #ifdef CONFIG_NAND_BOOT
95 #define CONFIG_SYS_FSL_PBL_RCW \
96         board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg
97 #endif
98
99 #ifdef CONFIG_SD_BOOT
100 #ifdef CONFIG_SD_BOOT_QSPI
101 #define CONFIG_SYS_FSL_PBL_RCW \
102         board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg
103 #else
104 #define CONFIG_SYS_FSL_PBL_RCW \
105         board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg
106 #endif
107 #endif
108
109 /* IFC */
110 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
111 #define CONFIG_FSL_IFC
112 /*
113  * CONFIG_SYS_FLASH_BASE has the final address (core view)
114  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
115  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
116  * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
117  */
118 #define CONFIG_SYS_FLASH_BASE                   0x60000000
119 #define CONFIG_SYS_FLASH_BASE_PHYS              CONFIG_SYS_FLASH_BASE
120 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY        0x00000000
121
122 #ifdef CONFIG_MTD_NOR_FLASH
123 #define CONFIG_FLASH_CFI_DRIVER
124 #define CONFIG_SYS_FLASH_CFI
125 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
126 #define CONFIG_SYS_FLASH_QUIET_TEST
127 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
128 #endif
129 #endif
130
131 /* LPUART */
132 #ifdef CONFIG_LPUART
133 #define CONFIG_LPUART_32B_REG
134 #define CFG_UART_MUX_MASK       0x6
135 #define CFG_UART_MUX_SHIFT      1
136 #define CFG_LPUART_EN           0x2
137 #endif
138
139 /* USB */
140 #define CONFIG_HAS_FSL_XHCI_USB
141 #ifdef CONFIG_HAS_FSL_XHCI_USB
142 #define CONFIG_USB_XHCI_HCD
143 #define CONFIG_USB_XHCI_FSL
144 #define CONFIG_USB_XHCI_DWC3
145 #define CONFIG_USB_MAX_CONTROLLER_COUNT         3
146 #define CONFIG_USB_STORAGE
147 #endif
148
149 /* SATA */
150 #define CONFIG_LIBATA
151 #define CONFIG_SCSI_AHCI
152 #define CONFIG_SCSI_AHCI_PLAT
153
154 /* EEPROM */
155 #define CONFIG_ID_EEPROM
156 #define CONFIG_SYS_I2C_EEPROM_NXID
157 #define CONFIG_SYS_EEPROM_BUS_NUM               0
158 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x57
159 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
160 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
161 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
162
163 #define CONFIG_SYS_SATA                         AHCI_BASE_ADDR
164
165 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
166 #define CONFIG_SYS_SCSI_MAX_LUN                 1
167 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
168                                                 CONFIG_SYS_SCSI_MAX_LUN)
169
170 /*
171  * IFC Definitions
172  */
173 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
174 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
175 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
176                                 CSPR_PORT_SIZE_16 | \
177                                 CSPR_MSEL_NOR | \
178                                 CSPR_V)
179 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
180 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
181                                 + 0x8000000) | \
182                                 CSPR_PORT_SIZE_16 | \
183                                 CSPR_MSEL_NOR | \
184                                 CSPR_V)
185 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
186
187 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
188                                         CSOR_NOR_TRHZ_80)
189 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
190                                         FTIM0_NOR_TEADC(0x5) | \
191                                         FTIM0_NOR_TEAHC(0x5))
192 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
193                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
194                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
195 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
196                                         FTIM2_NOR_TCH(0x4) | \
197                                         FTIM2_NOR_TWPH(0xe) | \
198                                         FTIM2_NOR_TWP(0x1c))
199 #define CONFIG_SYS_NOR_FTIM3            0
200
201 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
202 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
203 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
204 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
205
206 #define CONFIG_SYS_FLASH_EMPTY_INFO
207 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
208                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
209
210 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
211 #define CONFIG_SYS_WRITE_SWAPPED_DATA
212
213 /*
214  * NAND Flash Definitions
215  */
216 #define CONFIG_NAND_FSL_IFC
217
218 #define CONFIG_SYS_NAND_BASE            0x7e800000
219 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
220
221 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
222
223 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
224                                 | CSPR_PORT_SIZE_8      \
225                                 | CSPR_MSEL_NAND        \
226                                 | CSPR_V)
227 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
228 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
229                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
230                                 | CSOR_NAND_ECC_MODE_8  /* 8-bit ECC */ \
231                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
232                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
233                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
234                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
235
236 #define CONFIG_SYS_NAND_ONFI_DETECTION
237
238 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
239                                         FTIM0_NAND_TWP(0x18)   | \
240                                         FTIM0_NAND_TWCHT(0x7) | \
241                                         FTIM0_NAND_TWH(0xa))
242 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
243                                         FTIM1_NAND_TWBE(0x39)  | \
244                                         FTIM1_NAND_TRR(0xe)   | \
245                                         FTIM1_NAND_TRP(0x18))
246 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
247                                         FTIM2_NAND_TREH(0xa) | \
248                                         FTIM2_NAND_TWHRE(0x1e))
249 #define CONFIG_SYS_NAND_FTIM3           0x0
250
251 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
252 #define CONFIG_SYS_MAX_NAND_DEVICE      1
253 #define CONFIG_MTD_NAND_VERIFY_WRITE
254
255 #define CONFIG_SYS_NAND_BLOCK_SIZE      (256 * 1024)
256 #endif
257
258 #ifdef CONFIG_NAND_BOOT
259 #define CONFIG_SPL_PAD_TO               0x40000         /* block aligned */
260 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
261 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
262 #endif
263
264 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
265 #define CONFIG_QIXIS_I2C_ACCESS
266 #define CONFIG_SYS_I2C_EARLY_INIT
267 #endif
268
269 /*
270  * QIXIS Definitions
271  */
272 #define CONFIG_FSL_QIXIS
273
274 #ifdef CONFIG_FSL_QIXIS
275 #define QIXIS_BASE                      0x7fb00000
276 #define QIXIS_BASE_PHYS                 QIXIS_BASE
277 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
278 #define QIXIS_LBMAP_SWITCH              6
279 #define QIXIS_LBMAP_MASK                0x0f
280 #define QIXIS_LBMAP_SHIFT               0
281 #define QIXIS_LBMAP_DFLTBANK            0x00
282 #define QIXIS_LBMAP_ALTBANK             0x04
283 #define QIXIS_LBMAP_NAND                0x09
284 #define QIXIS_LBMAP_SD                  0x00
285 #define QIXIS_LBMAP_SD_QSPI             0xff
286 #define QIXIS_LBMAP_QSPI                0xff
287 #define QIXIS_RCW_SRC_NAND              0x110
288 #define QIXIS_RCW_SRC_SD                0x040
289 #define QIXIS_RCW_SRC_QSPI              0x045
290 #define QIXIS_RST_CTL_RESET             0x41
291 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
292 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
293 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
294
295 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
296 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
297                                         CSPR_PORT_SIZE_8 | \
298                                         CSPR_MSEL_GPCM | \
299                                         CSPR_V)
300 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
301 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
302                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
303                                         CSOR_NOR_TRHZ_80)
304
305 /*
306  * QIXIS Timing parameters for IFC GPCM
307  */
308 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xc) | \
309                                         FTIM0_GPCM_TEADC(0x20) | \
310                                         FTIM0_GPCM_TEAHC(0x10))
311 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0x50) | \
312                                         FTIM1_GPCM_TRAD(0x1f))
313 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0x8) | \
314                                         FTIM2_GPCM_TCH(0x8) | \
315                                         FTIM2_GPCM_TWP(0xf0))
316 #define CONFIG_SYS_FPGA_FTIM3           0x0
317 #endif
318
319 #ifdef CONFIG_NAND_BOOT
320 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
321 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
322 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
323 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
324 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
325 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
326 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
327 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
328 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
329 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
330 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
331 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
332 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
333 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
334 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
335 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
336 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
337 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
338 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
339 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
340 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
341 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
342 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
343 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
344 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
345 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
346 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
347 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
348 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
349 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
350 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
351 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
352 #else
353 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
354 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
355 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
356 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
357 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
358 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
359 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
360 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
361 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
362 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
363 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
364 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
365 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
366 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
367 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
368 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
369 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
370 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
371 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
372 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
373 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
374 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
375 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
376 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
377 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
378 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
379 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
380 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
381 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
382 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
383 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
384 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
385 #endif
386
387 /*
388  * I2C bus multiplexer
389  */
390 #define I2C_MUX_PCA_ADDR_PRI            0x77
391 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
392 #define I2C_RETIMER_ADDR                0x18
393 #define I2C_MUX_CH_DEFAULT              0x8
394 #define I2C_MUX_CH_CH7301               0xC
395 #define I2C_MUX_CH5                     0xD
396 #define I2C_MUX_CH6                     0xE
397 #define I2C_MUX_CH7                     0xF
398
399 #define I2C_MUX_CH_VOL_MONITOR 0xa
400
401 /* Voltage monitor on channel 2*/
402 #define I2C_VOL_MONITOR_ADDR           0x40
403 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
404 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
405 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
406
407 #define CONFIG_VID_FLS_ENV              "ls1046aqds_vdd_mv"
408 #ifndef CONFIG_SPL_BUILD
409 #define CONFIG_VID
410 #endif
411 #define CONFIG_VOL_MONITOR_IR36021_SET
412 #define CONFIG_VOL_MONITOR_INA220
413 /* The lowest and highest voltage allowed for LS1046AQDS */
414 #define VDD_MV_MIN                      819
415 #define VDD_MV_MAX                      1212
416
417 /*
418  * Miscellaneous configurable options
419  */
420 #define CONFIG_MISC_INIT_R
421 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
422 #define CONFIG_AUTO_COMPLETE
423 #define CONFIG_SYS_PBSIZE               \
424                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
425 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
426
427 #define CONFIG_SYS_MEMTEST_START        0x80000000
428 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
429
430 #define CONFIG_SYS_HZ                   1000
431
432 #define CONFIG_SYS_INIT_SP_OFFSET \
433         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
434
435 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
436
437 /*
438  * Environment
439  */
440 #define CONFIG_ENV_OVERWRITE
441
442 #ifdef CONFIG_NAND_BOOT
443 #define CONFIG_ENV_SIZE                 0x2000
444 #define CONFIG_ENV_OFFSET               (24 * CONFIG_SYS_NAND_BLOCK_SIZE)
445 #elif defined(CONFIG_SD_BOOT)
446 #define CONFIG_ENV_OFFSET               (3 * 1024 * 1024)
447 #define CONFIG_SYS_MMC_ENV_DEV          0
448 #define CONFIG_ENV_SIZE                 0x2000
449 #elif defined(CONFIG_QSPI_BOOT)
450 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
451 #define CONFIG_ENV_OFFSET               0x300000        /* 3MB */
452 #define CONFIG_ENV_SECT_SIZE            0x10000
453 #else
454 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x300000)
455 #define CONFIG_ENV_SECT_SIZE            0x20000
456 #define CONFIG_ENV_SIZE                 0x20000
457 #endif
458
459 #define CONFIG_CMDLINE_TAG
460
461 #undef CONFIG_BOOTCOMMAND
462 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
463 #define CONFIG_BOOTCOMMAND              "sf probe && sf read $kernel_load "    \
464                                         "e0000 f00000 && bootm $kernel_load"
465 #else
466 #define CONFIG_BOOTCOMMAND              "cp.b $kernel_start $kernel_load "     \
467                                         "$kernel_size && bootm $kernel_load"
468 #endif
469
470 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
471 #define MTDPARTS_DEFAULT "mtdparts=1550000.quadspi:2m(uboot)," \
472                         "14m(free)"
473 #else
474 #define MTDPARTS_DEFAULT "mtdparts=60000000.nor:" \
475                         "2m@0x100000(nor_bank0_uboot),"\
476                         "40m@0x1100000(nor_bank0_fit)," \
477                         "7m(nor_bank0_user)," \
478                         "2m@0x4100000(nor_bank4_uboot)," \
479                         "40m@0x5100000(nor_bank4_fit),"\
480                         "-(nor_bank4_user);" \
481                         "7e800000.flash:" \
482                         "4m(nand_uboot),36m(nand_kernel)," \
483                         "472m(nand_free);spi0.0:2m(uboot)," \
484                         "14m(free)"
485 #endif
486
487 #include <asm/fsl_secure_boot.h>
488
489 #endif /* __LS1046AQDS_H__ */