include/configs/ls1046aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __LS1046AQDS_H__
   7 #define __LS1046AQDS_H__
   8
   9 #include "ls1046a_common.h"
  10
  11 #ifndef __ASSEMBLY__
  12 unsigned long get_board_sys_clk(void);
  13 unsigned long get_board_ddr_clk(void);
  14 #endif
  15
  16 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  17 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
  18
  19 #define CONFIG_SKIP_LOWLEVEL_INIT
  20
  21 #define CONFIG_LAYERSCAPE_NS_ACCESS
  22
  23 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  24 /* Physical Memory Map */
  25 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  26
  27 #define CONFIG_DDR_SPD
  28 #define SPD_EEPROM_ADDRESS              0x51
  29 #define CONFIG_SYS_SPD_BUS_NUM          0
  30
  31 #define CONFIG_DDR_ECC
  32 #ifdef CONFIG_DDR_ECC
  33 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  34 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  35 #endif
  36
  37 /* DSPI */
  38 #ifdef CONFIG_FSL_DSPI
  39 #define CONFIG_SPI_FLASH_STMICRO        /* cs0 */
  40 #define CONFIG_SPI_FLASH_SST            /* cs1 */
  41 #define CONFIG_SPI_FLASH_EON            /* cs2 */
  42 #endif
  43
  44 #ifdef CONFIG_SYS_DPAA_FMAN
  45 #define RGMII_PHY1_ADDR         0x1
  46 #define RGMII_PHY2_ADDR         0x2
  47 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  48 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  49 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  50 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  51 /* PHY address on QSGMII riser card on slot 2 */
  52 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
  53 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
  54 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
  55 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
  56 #endif
  57
  58 #ifdef CONFIG_RAMBOOT_PBL
  59 #define CONFIG_SYS_FSL_PBL_PBI \
  60         board/freescale/ls1046aqds/ls1046aqds_pbi.cfg
  61 #endif
  62
  63 #ifdef CONFIG_NAND_BOOT
  64 #define CONFIG_SYS_FSL_PBL_RCW \
  65         board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg
  66 #endif
  67
  68 #ifdef CONFIG_SD_BOOT
  69 #ifdef CONFIG_SD_BOOT_QSPI
  70 #define CONFIG_SYS_FSL_PBL_RCW \
  71         board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg
  72 #else
  73 #define CONFIG_SYS_FSL_PBL_RCW \
  74         board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg
  75 #endif
  76 #endif
  77
  78 /* IFC */
  79 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  80 #define CONFIG_FSL_IFC
  81 /*
  82  * CONFIG_SYS_FLASH_BASE has the final address (core view)
  83  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
  84  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  85  * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
  86  */
  87 #define CONFIG_SYS_FLASH_BASE                   0x60000000
  88 #define CONFIG_SYS_FLASH_BASE_PHYS              CONFIG_SYS_FLASH_BASE
  89 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY        0x00000000
  90
  91 #ifdef CONFIG_MTD_NOR_FLASH
  92 #define CONFIG_SYS_FLASH_QUIET_TEST
  93 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
  94 #endif
  95 #endif
  96
  97 /* LPUART */
  98 #ifdef CONFIG_LPUART
  99 #define CONFIG_LPUART_32B_REG
 100 #define CFG_UART_MUX_MASK       0x6
 101 #define CFG_UART_MUX_SHIFT      1
 102 #define CFG_LPUART_EN           0x2
 103 #endif
 104
 105 /* EEPROM */
 106 #define CONFIG_SYS_I2C_EEPROM_NXID
 107 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 108
 109 /*
 110  * IFC Definitions
 111  */
 112 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 113 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
 114 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 115                                 CSPR_PORT_SIZE_16 | \
 116                                 CSPR_MSEL_NOR | \
 117                                 CSPR_V)
 118 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
 119 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 120                                 + 0x8000000) | \
 121                                 CSPR_PORT_SIZE_16 | \
 122                                 CSPR_MSEL_NOR | \
 123                                 CSPR_V)
 124 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 125
 126 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 127                                         CSOR_NOR_TRHZ_80)
 128 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 129                                         FTIM0_NOR_TEADC(0x5) | \
 130                                         FTIM0_NOR_TAVDS(0x6) | \
 131                                         FTIM0_NOR_TEAHC(0x5))
 132 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 133                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
 134                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 135 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x8) | \
 136                                         FTIM2_NOR_TCH(0x8) | \
 137                                         FTIM2_NOR_TWPH(0xe) | \
 138                                         FTIM2_NOR_TWP(0x1c))
 139 #define CONFIG_SYS_NOR_FTIM3            0
 140
 141 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 142 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 143 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 144 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 145
 146 #define CONFIG_SYS_FLASH_EMPTY_INFO
 147 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 148                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 149
 150 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 151 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 152
 153 /*
 154  * NAND Flash Definitions
 155  */
 156 #define CONFIG_NAND_FSL_IFC
 157
 158 #define CONFIG_SYS_NAND_BASE            0x7e800000
 159 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 160
 161 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 162
 163 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 164                                 | CSPR_PORT_SIZE_8      \
 165                                 | CSPR_MSEL_NAND        \
 166                                 | CSPR_V)
 167 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 168 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 169                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 170                                 | CSOR_NAND_ECC_MODE_8  /* 8-bit ECC */ \
 171                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 172                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 173                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 174                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 175
 176 #define CONFIG_SYS_NAND_ONFI_DETECTION
 177
 178 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 179                                         FTIM0_NAND_TWP(0x18)   | \
 180                                         FTIM0_NAND_TWCHT(0x7) | \
 181                                         FTIM0_NAND_TWH(0xa))
 182 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 183                                         FTIM1_NAND_TWBE(0x39)  | \
 184                                         FTIM1_NAND_TRR(0xe)   | \
 185                                         FTIM1_NAND_TRP(0x18))
 186 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 187                                         FTIM2_NAND_TREH(0xa) | \
 188                                         FTIM2_NAND_TWHRE(0x1e))
 189 #define CONFIG_SYS_NAND_FTIM3           0x0
 190
 191 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 192 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 193 #define CONFIG_MTD_NAND_VERIFY_WRITE
 194
 195 #define CONFIG_SYS_NAND_BLOCK_SIZE      (256 * 1024)
 196 #endif
 197
 198 #ifdef CONFIG_NAND_BOOT
 199 #define CONFIG_SPL_PAD_TO               0x40000         /* block aligned */
 200 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
 201 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
 202 #endif
 203
 204 #if defined(CONFIG_TFABOOT) || \
 205         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 206 #define CONFIG_QIXIS_I2C_ACCESS
 207 #endif
 208
 209 /*
 210  * QIXIS Definitions
 211  */
 212 #define CONFIG_FSL_QIXIS
 213
 214 #ifdef CONFIG_FSL_QIXIS
 215 #define QIXIS_BASE                      0x7fb00000
 216 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 217 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 218 #define QIXIS_LBMAP_SWITCH              6
 219 #define QIXIS_LBMAP_MASK                0x0f
 220 #define QIXIS_LBMAP_SHIFT               0
 221 #define QIXIS_LBMAP_DFLTBANK            0x00
 222 #define QIXIS_LBMAP_ALTBANK             0x04
 223 #define QIXIS_LBMAP_NAND                0x09
 224 #define QIXIS_LBMAP_SD                  0x00
 225 #define QIXIS_LBMAP_SD_QSPI             0xff
 226 #define QIXIS_LBMAP_QSPI                0xff
 227 #define QIXIS_RCW_SRC_NAND              0x110
 228 #define QIXIS_RCW_SRC_SD                0x040
 229 #define QIXIS_RCW_SRC_QSPI              0x045
 230 #define QIXIS_RST_CTL_RESET             0x41
 231 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 232 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 233 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 234
 235 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 236 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 237                                         CSPR_PORT_SIZE_8 | \
 238                                         CSPR_MSEL_GPCM | \
 239                                         CSPR_V)
 240 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 241 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 242                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 243                                         CSOR_NOR_TRHZ_80)
 244
 245 /*
 246  * QIXIS Timing parameters for IFC GPCM
 247  */
 248 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xc) | \
 249                                         FTIM0_GPCM_TEADC(0x20) | \
 250                                         FTIM0_GPCM_TEAHC(0x10))
 251 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0x50) | \
 252                                         FTIM1_GPCM_TRAD(0x1f))
 253 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0x8) | \
 254                                         FTIM2_GPCM_TCH(0x8) | \
 255                                         FTIM2_GPCM_TWP(0xf0))
 256 #define CONFIG_SYS_FPGA_FTIM3           0x0
 257 #endif
 258
 259 #ifdef CONFIG_TFABOOT
 260 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 261 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 262 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 263 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 264 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 265 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 266 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 267 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 268 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 269 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 270 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 271 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 272 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 273 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 274 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 275 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 276 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 277 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 278 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 279 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 280 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 281 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 282 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 283 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 284 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 285 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 286 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 287 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 288 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 289 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 290 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 291 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 292 #else
 293 #ifdef CONFIG_NAND_BOOT
 294 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 295 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 296 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 297 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 298 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 299 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 300 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 301 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 302 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 303 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 304 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 305 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 306 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 307 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 308 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 309 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 310 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 311 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 312 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 313 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 314 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 315 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 316 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 317 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 318 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 319 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 320 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 321 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 322 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 323 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 324 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 325 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 326 #else
 327 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 328 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 329 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 330 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 331 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 332 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 333 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 334 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 335 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 336 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 337 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 338 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 339 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 340 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 341 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 342 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 343 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 344 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 345 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 346 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 347 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 348 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 349 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 350 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 351 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 352 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 353 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 354 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 355 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 356 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 357 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 358 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 359 #endif
 360 #endif
 361
 362 /*
 363  * I2C bus multiplexer
 364  */
 365 #define I2C_MUX_PCA_ADDR_PRI            0x77
 366 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 367 #define I2C_RETIMER_ADDR                0x18
 368 #define I2C_MUX_CH_DEFAULT              0x8
 369 #define I2C_MUX_CH_CH7301               0xC
 370 #define I2C_MUX_CH5                     0xD
 371 #define I2C_MUX_CH6                     0xE
 372 #define I2C_MUX_CH7                     0xF
 373
 374 #define I2C_MUX_CH_VOL_MONITOR 0xa
 375
 376 /* Voltage monitor on channel 2*/
 377 #define I2C_VOL_MONITOR_ADDR           0x40
 378 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 379 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 380 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 381
 382 #define CONFIG_VID_FLS_ENV              "ls1046aqds_vdd_mv"
 383 #ifndef CONFIG_SPL_BUILD
 384 #define CONFIG_VID
 385 #endif
 386 #define CONFIG_VOL_MONITOR_IR36021_SET
 387 #define CONFIG_VOL_MONITOR_INA220
 388 /* The lowest and highest voltage allowed for LS1046AQDS */
 389 #define VDD_MV_MIN                      819
 390 #define VDD_MV_MAX                      1212
 391
 392 /*
 393  * Miscellaneous configurable options
 394  */
 395
 396 #define CONFIG_SYS_HZ                   1000
 397
 398 #define CONFIG_SYS_INIT_SP_OFFSET \
 399         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 400
 401 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 402
 403 /*
 404  * Environment
 405  */
 406
 407 #define CONFIG_CMDLINE_TAG
 408
 409 #undef CONFIG_BOOTCOMMAND
 410 #ifdef CONFIG_TFABOOT
 411 #define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; "   \
 412                            "env exists secureboot && esbc_halt;;"
 413 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd"      \
 414                            "env exists secureboot && esbc_halt;;"
 415 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "     \
 416                            "env exists secureboot && esbc_halt;;"
 417 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "   \
 418                            "env exists secureboot && esbc_halt;;"
 419 #else
 420 #if defined(CONFIG_QSPI_BOOT)
 421 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "      \
 422                            "env exists secureboot && esbc_halt;;"
 423 #elif defined(CONFIG_NAND_BOOT)
 424 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; "     \
 425                            "env exists secureboot && esbc_halt;;"
 426 #elif defined(CONFIG_SD_BOOT)
 427 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "       \
 428                            "env exists secureboot && esbc_halt;;"
 429 #else
 430 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "      \
 431                            "env exists secureboot && esbc_halt;;"
 432 #endif
 433 #endif
 434
 435 #include <asm/fsl_secure_boot.h>
 436
 437 #endif /* __LS1046AQDS_H__ */