1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016 Freescale Semiconductor, Inc.
6 #ifndef __LS1046AQDS_H__
7 #define __LS1046AQDS_H__
9 #include "ls1046a_common.h"
11 #define CONFIG_LAYERSCAPE_NS_ACCESS
13 /* Physical Memory Map */
15 #define SPD_EEPROM_ADDRESS 0x51
16 #define CONFIG_SYS_SPD_BUS_NUM 0
19 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
22 #ifdef CONFIG_SYS_DPAA_FMAN
23 #define RGMII_PHY1_ADDR 0x1
24 #define RGMII_PHY2_ADDR 0x2
25 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
26 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
27 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
28 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
29 /* PHY address on QSGMII riser card on slot 2 */
30 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
31 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
32 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
33 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
37 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
39 * CONFIG_SYS_FLASH_BASE has the final address (core view)
40 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
41 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
42 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
44 #define CONFIG_SYS_FLASH_BASE 0x60000000
45 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
46 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
48 #ifdef CONFIG_MTD_NOR_FLASH
49 #define CONFIG_SYS_FLASH_QUIET_TEST
50 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
56 #define CFG_UART_MUX_MASK 0x6
57 #define CFG_UART_MUX_SHIFT 1
58 #define CFG_LPUART_EN 0x2
62 #define CONFIG_SYS_I2C_EEPROM_NXID
63 #define CONFIG_SYS_EEPROM_BUS_NUM 0
68 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
69 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
70 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
74 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
75 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
80 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
82 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
84 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
85 FTIM0_NOR_TEADC(0x5) | \
86 FTIM0_NOR_TAVDS(0x6) | \
88 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
89 FTIM1_NOR_TRAD_NOR(0x1a) | \
90 FTIM1_NOR_TSEQRAD_NOR(0x13))
91 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \
92 FTIM2_NOR_TCH(0x8) | \
93 FTIM2_NOR_TWPH(0xe) | \
95 #define CONFIG_SYS_NOR_FTIM3 0
97 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
98 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
99 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
101 #define CONFIG_SYS_FLASH_EMPTY_INFO
102 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
103 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
105 #define CONFIG_SYS_WRITE_SWAPPED_DATA
108 * NAND Flash Definitions
111 #define CONFIG_SYS_NAND_BASE 0x7e800000
112 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
114 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
116 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
120 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
121 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
122 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
123 | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
124 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
125 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
126 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
127 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
129 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
130 FTIM0_NAND_TWP(0x18) | \
131 FTIM0_NAND_TWCHT(0x7) | \
133 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
134 FTIM1_NAND_TWBE(0x39) | \
135 FTIM1_NAND_TRR(0xe) | \
136 FTIM1_NAND_TRP(0x18))
137 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
138 FTIM2_NAND_TREH(0xa) | \
139 FTIM2_NAND_TWHRE(0x1e))
140 #define CONFIG_SYS_NAND_FTIM3 0x0
142 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
143 #define CONFIG_SYS_MAX_NAND_DEVICE 1
144 #define CONFIG_MTD_NAND_VERIFY_WRITE
147 #ifdef CONFIG_NAND_BOOT
148 #define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */
149 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
152 #if defined(CONFIG_TFABOOT) || \
153 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
154 #define CONFIG_QIXIS_I2C_ACCESS
160 #define CONFIG_FSL_QIXIS
162 #ifdef CONFIG_FSL_QIXIS
163 #define QIXIS_BASE 0x7fb00000
164 #define QIXIS_BASE_PHYS QIXIS_BASE
165 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
166 #define QIXIS_LBMAP_SWITCH 6
167 #define QIXIS_LBMAP_MASK 0x0f
168 #define QIXIS_LBMAP_SHIFT 0
169 #define QIXIS_LBMAP_DFLTBANK 0x00
170 #define QIXIS_LBMAP_ALTBANK 0x04
171 #define QIXIS_LBMAP_NAND 0x09
172 #define QIXIS_LBMAP_SD 0x00
173 #define QIXIS_LBMAP_SD_QSPI 0xff
174 #define QIXIS_LBMAP_QSPI 0xff
175 #define QIXIS_RCW_SRC_NAND 0x110
176 #define QIXIS_RCW_SRC_SD 0x040
177 #define QIXIS_RCW_SRC_QSPI 0x045
178 #define QIXIS_RST_CTL_RESET 0x41
179 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
180 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
181 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
183 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
184 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
188 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
189 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
190 CSOR_NOR_NOR_MODE_AVD_NOR | \
194 * QIXIS Timing parameters for IFC GPCM
196 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
197 FTIM0_GPCM_TEADC(0x20) | \
198 FTIM0_GPCM_TEAHC(0x10))
199 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
200 FTIM1_GPCM_TRAD(0x1f))
201 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
202 FTIM2_GPCM_TCH(0x8) | \
203 FTIM2_GPCM_TWP(0xf0))
204 #define CONFIG_SYS_FPGA_FTIM3 0x0
207 #ifdef CONFIG_TFABOOT
208 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
209 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
210 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
211 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
212 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
213 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
214 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
215 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
216 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
217 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
218 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
219 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
220 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
221 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
222 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
223 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
224 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
225 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
226 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
227 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
228 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
229 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
230 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
231 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
232 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
233 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
234 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
235 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
236 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
237 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
238 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
239 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
241 #ifdef CONFIG_NAND_BOOT
242 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
243 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
244 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
245 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
246 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
247 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
248 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
249 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
250 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
251 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
252 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
253 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
254 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
255 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
256 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
257 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
258 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
259 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
260 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
261 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
262 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
263 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
264 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
265 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
266 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
267 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
268 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
269 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
270 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
271 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
272 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
273 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
275 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
276 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
277 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
278 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
279 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
280 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
281 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
282 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
283 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
284 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
285 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
286 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
287 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
288 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
289 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
290 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
291 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
292 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
293 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
294 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
295 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
296 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
297 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
298 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
299 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
300 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
301 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
302 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
303 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
304 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
305 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
306 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
311 * I2C bus multiplexer
313 #define I2C_MUX_PCA_ADDR_PRI 0x77
314 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
315 #define I2C_RETIMER_ADDR 0x18
316 #define I2C_MUX_CH_DEFAULT 0x8
317 #define I2C_MUX_CH_CH7301 0xC
318 #define I2C_MUX_CH5 0xD
319 #define I2C_MUX_CH6 0xE
320 #define I2C_MUX_CH7 0xF
322 #define I2C_MUX_CH_VOL_MONITOR 0xa
324 /* Voltage monitor on channel 2*/
325 #define I2C_VOL_MONITOR_ADDR 0x40
326 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
327 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
328 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
330 /* The lowest and highest voltage allowed for LS1046AQDS */
331 #define VDD_MV_MIN 819
332 #define VDD_MV_MAX 1212
335 * Miscellaneous configurable options
338 #define CONFIG_SYS_INIT_SP_OFFSET \
339 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
345 #ifdef CONFIG_TFABOOT
346 #define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \
347 "env exists secureboot && esbc_halt;;"
348 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd" \
349 "env exists secureboot && esbc_halt;;"
350 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
351 "env exists secureboot && esbc_halt;;"
352 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
353 "env exists secureboot && esbc_halt;;"
356 #include <asm/fsl_secure_boot.h>
358 #endif /* __LS1046AQDS_H__ */