include/configs/ls1046aqds.h

   1 /*
   2  * Copyright 2016 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS1046AQDS_H__
   8 #define __LS1046AQDS_H__
   9
  10 #include "ls1046a_common.h"
  11
  12 #define CONFIG_DISPLAY_CPUINFO
  13 #define CONFIG_DISPLAY_BOARDINFO
  14
  15 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
  16 #define CONFIG_SYS_TEXT_BASE            0x82000000
  17 #elif defined(CONFIG_QSPI_BOOT)
  18 #define CONFIG_SYS_TEXT_BASE            0x40010000
  19 #else
  20 #define CONFIG_SYS_TEXT_BASE            0x60100000
  21 #endif
  22
  23 #ifndef __ASSEMBLY__
  24 unsigned long get_board_sys_clk(void);
  25 unsigned long get_board_ddr_clk(void);
  26 #endif
  27
  28 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  29 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
  30
  31 #define CONFIG_SKIP_LOWLEVEL_INIT
  32
  33 #define CONFIG_LAYERSCAPE_NS_ACCESS
  34
  35 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  36 /* Physical Memory Map */
  37 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  38 #define CONFIG_NR_DRAM_BANKS            2
  39
  40 #define CONFIG_DDR_SPD
  41 #define SPD_EEPROM_ADDRESS              0x51
  42 #define CONFIG_SYS_SPD_BUS_NUM          0
  43
  44 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
  45
  46 #define CONFIG_DDR_ECC
  47 #ifdef CONFIG_DDR_ECC
  48 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  49 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  50 #endif
  51
  52 #define CONFIG_SYS_HAS_SERDES
  53
  54 /* DSPI */
  55 #ifdef CONFIG_FSL_DSPI
  56 #define CONFIG_SPI_FLASH_STMICRO        /* cs0 */
  57 #define CONFIG_SPI_FLASH_SST            /* cs1 */
  58 #define CONFIG_SPI_FLASH_EON            /* cs2 */
  59 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  60 #define CONFIG_SF_DEFAULT_BUS           1
  61 #define CONFIG_SF_DEFAULT_CS            0
  62 #endif
  63 #endif
  64
  65 /* QSPI */
  66 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  67 #ifdef CONFIG_FSL_QSPI
  68 #define CONFIG_SPI_FLASH_SPANSION
  69 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
  70 #define FSL_QSPI_FLASH_NUM              2
  71 #endif
  72 #endif
  73
  74 #ifdef CONFIG_SYS_DPAA_FMAN
  75 #define CONFIG_FMAN_ENET
  76 #define CONFIG_PHYLIB
  77 #define CONFIG_PHY_VITESSE
  78 #define CONFIG_PHY_REALTEK
  79 #define CONFIG_PHYLIB_10G
  80 #define RGMII_PHY1_ADDR         0x1
  81 #define RGMII_PHY2_ADDR         0x2
  82 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  83 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  84 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  85 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  86 /* PHY address on QSGMII riser card on slot 2 */
  87 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
  88 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
  89 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
  90 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
  91 #endif
  92
  93 #ifdef CONFIG_RAMBOOT_PBL
  94 #define CONFIG_SYS_FSL_PBL_PBI \
  95         board/freescale/ls1046aqds/ls1046aqds_pbi.cfg
  96 #endif
  97
  98 #ifdef CONFIG_NAND_BOOT
  99 #define CONFIG_SYS_FSL_PBL_RCW \
 100         board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg
 101 #endif
 102
 103 #ifdef CONFIG_SD_BOOT
 104 #ifdef CONFIG_SD_BOOT_QSPI
 105 #define CONFIG_SYS_FSL_PBL_RCW \
 106         board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg
 107 #else
 108 #define CONFIG_SYS_FSL_PBL_RCW \
 109         board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg
 110 #endif
 111 #endif
 112
 113 /* IFC */
 114 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 115 #define CONFIG_FSL_IFC
 116 /*
 117  * CONFIG_SYS_FLASH_BASE has the final address (core view)
 118  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
 119  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
 120  * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
 121  */
 122 #define CONFIG_SYS_FLASH_BASE                   0x60000000
 123 #define CONFIG_SYS_FLASH_BASE_PHYS              CONFIG_SYS_FLASH_BASE
 124 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY        0x00000000
 125
 126 #ifndef CONFIG_SYS_NO_FLASH
 127 #define CONFIG_FLASH_CFI_DRIVER
 128 #define CONFIG_SYS_FLASH_CFI
 129 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 130 #define CONFIG_SYS_FLASH_QUIET_TEST
 131 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 132 #endif
 133 #endif
 134
 135 /* SATA */
 136 #define CONFIG_LIBATA
 137 #define CONFIG_SCSI_AHCI
 138 #define CONFIG_SCSI_AHCI_PLAT
 139 #define CONFIG_SCSI
 140 #define CONFIG_DOS_PARTITION
 141 #define CONFIG_BOARD_LATE_INIT
 142
 143 /* EEPROM */
 144 #define CONFIG_ID_EEPROM
 145 #define CONFIG_SYS_I2C_EEPROM_NXID
 146 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 147 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x57
 148 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 149 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 150 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 151
 152 #define CONFIG_SYS_SATA                         AHCI_BASE_ADDR
 153
 154 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
 155 #define CONFIG_SYS_SCSI_MAX_LUN                 1
 156 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 157                                                 CONFIG_SYS_SCSI_MAX_LUN)
 158
 159 /*
 160  * IFC Definitions
 161  */
 162 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 163 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
 164 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 165                                 CSPR_PORT_SIZE_16 | \
 166                                 CSPR_MSEL_NOR | \
 167                                 CSPR_V)
 168 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
 169 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 170                                 + 0x8000000) | \
 171                                 CSPR_PORT_SIZE_16 | \
 172                                 CSPR_MSEL_NOR | \
 173                                 CSPR_V)
 174 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 175
 176 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 177                                         CSOR_NOR_TRHZ_80)
 178 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 179                                         FTIM0_NOR_TEADC(0x5) | \
 180                                         FTIM0_NOR_TEAHC(0x5))
 181 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 182                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
 183                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 184 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 185                                         FTIM2_NOR_TCH(0x4) | \
 186                                         FTIM2_NOR_TWPH(0xe) | \
 187                                         FTIM2_NOR_TWP(0x1c))
 188 #define CONFIG_SYS_NOR_FTIM3            0
 189
 190 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 191 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 192 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 193 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 194
 195 #define CONFIG_SYS_FLASH_EMPTY_INFO
 196 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 197                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 198
 199 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 200 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 201
 202 /*
 203  * NAND Flash Definitions
 204  */
 205 #define CONFIG_NAND_FSL_IFC
 206
 207 #define CONFIG_SYS_NAND_BASE            0x7e800000
 208 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 209
 210 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 211
 212 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 213                                 | CSPR_PORT_SIZE_8      \
 214                                 | CSPR_MSEL_NAND        \
 215                                 | CSPR_V)
 216 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 217 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 218                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 219                                 | CSOR_NAND_ECC_MODE_8  /* 8-bit ECC */ \
 220                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 221                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 222                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 223                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 224
 225 #define CONFIG_SYS_NAND_ONFI_DETECTION
 226
 227 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 228                                         FTIM0_NAND_TWP(0x18)   | \
 229                                         FTIM0_NAND_TWCHT(0x7) | \
 230                                         FTIM0_NAND_TWH(0xa))
 231 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 232                                         FTIM1_NAND_TWBE(0x39)  | \
 233                                         FTIM1_NAND_TRR(0xe)   | \
 234                                         FTIM1_NAND_TRP(0x18))
 235 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 236                                         FTIM2_NAND_TREH(0xa) | \
 237                                         FTIM2_NAND_TWHRE(0x1e))
 238 #define CONFIG_SYS_NAND_FTIM3           0x0
 239
 240 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 241 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 242 #define CONFIG_MTD_NAND_VERIFY_WRITE
 243 #define CONFIG_CMD_NAND
 244
 245 #define CONFIG_SYS_NAND_BLOCK_SIZE      (256 * 1024)
 246 #endif
 247
 248 #ifdef CONFIG_NAND_BOOT
 249 #define CONFIG_SPL_PAD_TO               0x40000         /* block aligned */
 250 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
 251 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
 252 #endif
 253
 254 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 255 #define CONFIG_QIXIS_I2C_ACCESS
 256 #define CONFIG_SYS_I2C_EARLY_INIT
 257 #define CONFIG_SYS_NO_FLASH
 258 #endif
 259
 260 /*
 261  * QIXIS Definitions
 262  */
 263 #define CONFIG_FSL_QIXIS
 264
 265 #ifdef CONFIG_FSL_QIXIS
 266 #define QIXIS_BASE                      0x7fb00000
 267 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 268 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 269 #define QIXIS_LBMAP_SWITCH              6
 270 #define QIXIS_LBMAP_MASK                0x0f
 271 #define QIXIS_LBMAP_SHIFT               0
 272 #define QIXIS_LBMAP_DFLTBANK            0x00
 273 #define QIXIS_LBMAP_ALTBANK             0x04
 274 #define QIXIS_LBMAP_NAND                0x09
 275 #define QIXIS_LBMAP_SD                  0x00
 276 #define QIXIS_LBMAP_SD_QSPI             0xff
 277 #define QIXIS_LBMAP_QSPI                0xff
 278 #define QIXIS_RCW_SRC_NAND              0x110
 279 #define QIXIS_RCW_SRC_SD                0x040
 280 #define QIXIS_RCW_SRC_QSPI              0x045
 281 #define QIXIS_RST_CTL_RESET             0x41
 282 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 283 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 284 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 285
 286 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 287 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 288                                         CSPR_PORT_SIZE_8 | \
 289                                         CSPR_MSEL_GPCM | \
 290                                         CSPR_V)
 291 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 292 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 293                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 294                                         CSOR_NOR_TRHZ_80)
 295
 296 /*
 297  * QIXIS Timing parameters for IFC GPCM
 298  */
 299 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xc) | \
 300                                         FTIM0_GPCM_TEADC(0x20) | \
 301                                         FTIM0_GPCM_TEAHC(0x10))
 302 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0x50) | \
 303                                         FTIM1_GPCM_TRAD(0x1f))
 304 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0x8) | \
 305                                         FTIM2_GPCM_TCH(0x8) | \
 306                                         FTIM2_GPCM_TWP(0xf0))
 307 #define CONFIG_SYS_FPGA_FTIM3           0x0
 308 #endif
 309
 310 #ifdef CONFIG_NAND_BOOT
 311 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 312 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 313 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 314 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 315 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 316 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 317 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 318 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 319 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 320 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 321 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 322 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 323 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 324 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 325 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 326 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 327 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 328 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 329 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 330 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 331 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 332 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 333 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 334 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 335 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 336 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 337 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 338 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 339 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 340 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 341 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 342 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 343 #else
 344 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 345 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 346 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 347 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 348 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 349 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 350 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 351 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 352 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 353 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 354 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 355 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 356 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 357 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 358 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 359 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 360 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 361 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 362 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 363 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 364 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 365 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 366 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 367 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 368 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 369 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 370 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 371 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 372 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 373 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 374 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 375 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 376 #endif
 377
 378 /*
 379  * I2C bus multiplexer
 380  */
 381 #define I2C_MUX_PCA_ADDR_PRI            0x77
 382 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 383 #define I2C_RETIMER_ADDR                0x18
 384 #define I2C_MUX_CH_DEFAULT              0x8
 385 #define I2C_MUX_CH_CH7301               0xC
 386 #define I2C_MUX_CH5                     0xD
 387 #define I2C_MUX_CH6                     0xE
 388 #define I2C_MUX_CH7                     0xF
 389
 390 #define I2C_MUX_CH_VOL_MONITOR 0xa
 391
 392 /* Voltage monitor on channel 2*/
 393 #define I2C_VOL_MONITOR_ADDR           0x40
 394 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 395 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 396 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 397
 398 #define CONFIG_VID_FLS_ENV              "ls1046aqds_vdd_mv"
 399 #ifndef CONFIG_SPL_BUILD
 400 #define CONFIG_VID
 401 #endif
 402 #define CONFIG_VOL_MONITOR_IR36021_SET
 403 #define CONFIG_VOL_MONITOR_INA220
 404 /* The lowest and highest voltage allowed for LS1046AQDS */
 405 #define VDD_MV_MIN                      819
 406 #define VDD_MV_MAX                      1212
 407
 408 /*
 409  * Miscellaneous configurable options
 410  */
 411 #define CONFIG_MISC_INIT_R
 412 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 413 #define CONFIG_AUTO_COMPLETE
 414 #define CONFIG_SYS_PBSIZE               \
 415                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 416 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 417
 418 #define CONFIG_SYS_MEMTEST_START        0x80000000
 419 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
 420
 421 #define CONFIG_SYS_HZ                   1000
 422
 423 /*
 424  * Stack sizes
 425  * The stack sizes are set up in start.S using the settings below
 426  */
 427 #define CONFIG_STACKSIZE                (30 * 1024)
 428
 429 #define CONFIG_SYS_INIT_SP_OFFSET \
 430         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 431
 432 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 433
 434 /*
 435  * Environment
 436  */
 437 #define CONFIG_ENV_OVERWRITE
 438
 439 #ifdef CONFIG_NAND_BOOT
 440 #define CONFIG_ENV_IS_IN_NAND
 441 #define CONFIG_ENV_SIZE                 0x2000
 442 #define CONFIG_ENV_OFFSET               (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
 443 #elif defined(CONFIG_SD_BOOT)
 444 #define CONFIG_ENV_OFFSET               (1024 * 1024)
 445 #define CONFIG_ENV_IS_IN_MMC
 446 #define CONFIG_SYS_MMC_ENV_DEV          0
 447 #define CONFIG_ENV_SIZE                 0x2000
 448 #elif defined(CONFIG_QSPI_BOOT)
 449 #define CONFIG_ENV_IS_IN_SPI_FLASH
 450 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 451 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 452 #define CONFIG_ENV_SECT_SIZE            0x10000
 453 #else
 454 #define CONFIG_ENV_IS_IN_FLASH
 455 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x200000)
 456 #define CONFIG_ENV_SECT_SIZE            0x20000
 457 #define CONFIG_ENV_SIZE                 0x20000
 458 #endif
 459
 460 #define CONFIG_CMDLINE_TAG
 461
 462 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 463 #define CONFIG_BOOTCOMMAND              "sf probe && sf read $kernel_load "    \
 464                                         "e0000 f00000 && bootm $kernel_load"
 465 #else
 466 #define CONFIG_BOOTCOMMAND              "cp.b $kernel_start $kernel_load "     \
 467                                         "$kernel_size && bootm $kernel_load"
 468 #endif
 469
 470 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 471 #define MTDPARTS_DEFAULT "mtdparts=1550000.quadspi:2m(uboot)," \
 472                         "14m(free)"
 473 #else
 474 #define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \
 475                         "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \
 476                         "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \
 477                         "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \
 478                         "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \
 479                         "40m(nor_bank4_fit);7e800000.flash:" \
 480                         "4m(nand_uboot),36m(nand_kernel)," \
 481                         "472m(nand_free);spi0.0:2m(uboot)," \
 482                         "14m(free)"
 483 #endif
 484
 485 #include <asm/fsl_secure_boot.h>
 486
 487 #endif /* __LS1046AQDS_H__ */