include/configs/ls1046aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __LS1046AQDS_H__
   7 #define __LS1046AQDS_H__
   8
   9 #include "ls1046a_common.h"
  10
  11 #ifndef __ASSEMBLY__
  12 unsigned long get_board_sys_clk(void);
  13 #endif
  14
  15 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  16
  17 #define CONFIG_SKIP_LOWLEVEL_INIT
  18
  19 #define CONFIG_LAYERSCAPE_NS_ACCESS
  20
  21 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  22 /* Physical Memory Map */
  23 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  24
  25 #define CONFIG_DDR_SPD
  26 #define SPD_EEPROM_ADDRESS              0x51
  27 #define CONFIG_SYS_SPD_BUS_NUM          0
  28
  29 #define CONFIG_DDR_ECC
  30 #ifdef CONFIG_DDR_ECC
  31 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  32 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  33 #endif
  34
  35 /* DSPI */
  36 #ifdef CONFIG_FSL_DSPI
  37 #define CONFIG_SPI_FLASH_STMICRO        /* cs0 */
  38 #define CONFIG_SPI_FLASH_SST            /* cs1 */
  39 #define CONFIG_SPI_FLASH_EON            /* cs2 */
  40 #endif
  41
  42 #ifdef CONFIG_SYS_DPAA_FMAN
  43 #define RGMII_PHY1_ADDR         0x1
  44 #define RGMII_PHY2_ADDR         0x2
  45 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  46 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  47 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  48 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  49 /* PHY address on QSGMII riser card on slot 2 */
  50 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
  51 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
  52 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
  53 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
  54 #endif
  55
  56 #ifdef CONFIG_RAMBOOT_PBL
  57 #define CONFIG_SYS_FSL_PBL_PBI \
  58         board/freescale/ls1046aqds/ls1046aqds_pbi.cfg
  59 #endif
  60
  61 #ifdef CONFIG_NAND_BOOT
  62 #define CONFIG_SYS_FSL_PBL_RCW \
  63         board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg
  64 #endif
  65
  66 #ifdef CONFIG_SD_BOOT
  67 #ifdef CONFIG_SD_BOOT_QSPI
  68 #define CONFIG_SYS_FSL_PBL_RCW \
  69         board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg
  70 #else
  71 #define CONFIG_SYS_FSL_PBL_RCW \
  72         board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg
  73 #endif
  74 #endif
  75
  76 /* IFC */
  77 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  78 #define CONFIG_FSL_IFC
  79 /*
  80  * CONFIG_SYS_FLASH_BASE has the final address (core view)
  81  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
  82  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  83  * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
  84  */
  85 #define CONFIG_SYS_FLASH_BASE                   0x60000000
  86 #define CONFIG_SYS_FLASH_BASE_PHYS              CONFIG_SYS_FLASH_BASE
  87 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY        0x00000000
  88
  89 #ifdef CONFIG_MTD_NOR_FLASH
  90 #define CONFIG_SYS_FLASH_QUIET_TEST
  91 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
  92 #endif
  93 #endif
  94
  95 /* LPUART */
  96 #ifdef CONFIG_LPUART
  97 #define CONFIG_LPUART_32B_REG
  98 #define CFG_UART_MUX_MASK       0x6
  99 #define CFG_UART_MUX_SHIFT      1
 100 #define CFG_LPUART_EN           0x2
 101 #endif
 102
 103 /* EEPROM */
 104 #define CONFIG_SYS_I2C_EEPROM_NXID
 105 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 106
 107 /*
 108  * IFC Definitions
 109  */
 110 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 111 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
 112 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 113                                 CSPR_PORT_SIZE_16 | \
 114                                 CSPR_MSEL_NOR | \
 115                                 CSPR_V)
 116 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
 117 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 118                                 + 0x8000000) | \
 119                                 CSPR_PORT_SIZE_16 | \
 120                                 CSPR_MSEL_NOR | \
 121                                 CSPR_V)
 122 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 123
 124 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 125                                         CSOR_NOR_TRHZ_80)
 126 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 127                                         FTIM0_NOR_TEADC(0x5) | \
 128                                         FTIM0_NOR_TAVDS(0x6) | \
 129                                         FTIM0_NOR_TEAHC(0x5))
 130 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 131                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
 132                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 133 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x8) | \
 134                                         FTIM2_NOR_TCH(0x8) | \
 135                                         FTIM2_NOR_TWPH(0xe) | \
 136                                         FTIM2_NOR_TWP(0x1c))
 137 #define CONFIG_SYS_NOR_FTIM3            0
 138
 139 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 140 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 141 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 142 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 143
 144 #define CONFIG_SYS_FLASH_EMPTY_INFO
 145 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 146                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 147
 148 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 149 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 150
 151 /*
 152  * NAND Flash Definitions
 153  */
 154 #define CONFIG_NAND_FSL_IFC
 155
 156 #define CONFIG_SYS_NAND_BASE            0x7e800000
 157 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 158
 159 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 160
 161 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 162                                 | CSPR_PORT_SIZE_8      \
 163                                 | CSPR_MSEL_NAND        \
 164                                 | CSPR_V)
 165 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 166 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 167                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 168                                 | CSOR_NAND_ECC_MODE_8  /* 8-bit ECC */ \
 169                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 170                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 171                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 172                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 173
 174 #define CONFIG_SYS_NAND_ONFI_DETECTION
 175
 176 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 177                                         FTIM0_NAND_TWP(0x18)   | \
 178                                         FTIM0_NAND_TWCHT(0x7) | \
 179                                         FTIM0_NAND_TWH(0xa))
 180 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 181                                         FTIM1_NAND_TWBE(0x39)  | \
 182                                         FTIM1_NAND_TRR(0xe)   | \
 183                                         FTIM1_NAND_TRP(0x18))
 184 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 185                                         FTIM2_NAND_TREH(0xa) | \
 186                                         FTIM2_NAND_TWHRE(0x1e))
 187 #define CONFIG_SYS_NAND_FTIM3           0x0
 188
 189 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 190 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 191 #define CONFIG_MTD_NAND_VERIFY_WRITE
 192
 193 #define CONFIG_SYS_NAND_BLOCK_SIZE      (256 * 1024)
 194 #endif
 195
 196 #ifdef CONFIG_NAND_BOOT
 197 #define CONFIG_SPL_PAD_TO               0x40000         /* block aligned */
 198 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
 199 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
 200 #endif
 201
 202 #if defined(CONFIG_TFABOOT) || \
 203         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 204 #define CONFIG_QIXIS_I2C_ACCESS
 205 #endif
 206
 207 /*
 208  * QIXIS Definitions
 209  */
 210 #define CONFIG_FSL_QIXIS
 211
 212 #ifdef CONFIG_FSL_QIXIS
 213 #define QIXIS_BASE                      0x7fb00000
 214 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 215 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 216 #define QIXIS_LBMAP_SWITCH              6
 217 #define QIXIS_LBMAP_MASK                0x0f
 218 #define QIXIS_LBMAP_SHIFT               0
 219 #define QIXIS_LBMAP_DFLTBANK            0x00
 220 #define QIXIS_LBMAP_ALTBANK             0x04
 221 #define QIXIS_LBMAP_NAND                0x09
 222 #define QIXIS_LBMAP_SD                  0x00
 223 #define QIXIS_LBMAP_SD_QSPI             0xff
 224 #define QIXIS_LBMAP_QSPI                0xff
 225 #define QIXIS_RCW_SRC_NAND              0x110
 226 #define QIXIS_RCW_SRC_SD                0x040
 227 #define QIXIS_RCW_SRC_QSPI              0x045
 228 #define QIXIS_RST_CTL_RESET             0x41
 229 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 230 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 231 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 232
 233 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 234 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 235                                         CSPR_PORT_SIZE_8 | \
 236                                         CSPR_MSEL_GPCM | \
 237                                         CSPR_V)
 238 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 239 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 240                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 241                                         CSOR_NOR_TRHZ_80)
 242
 243 /*
 244  * QIXIS Timing parameters for IFC GPCM
 245  */
 246 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xc) | \
 247                                         FTIM0_GPCM_TEADC(0x20) | \
 248                                         FTIM0_GPCM_TEAHC(0x10))
 249 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0x50) | \
 250                                         FTIM1_GPCM_TRAD(0x1f))
 251 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0x8) | \
 252                                         FTIM2_GPCM_TCH(0x8) | \
 253                                         FTIM2_GPCM_TWP(0xf0))
 254 #define CONFIG_SYS_FPGA_FTIM3           0x0
 255 #endif
 256
 257 #ifdef CONFIG_TFABOOT
 258 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 259 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 260 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 261 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 262 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 263 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 264 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 265 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 266 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 267 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 268 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 269 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 270 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 271 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 272 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 273 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 274 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 275 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 276 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 277 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 278 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 279 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 280 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 281 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 282 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 283 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 284 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 285 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 286 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 287 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 288 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 289 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 290 #else
 291 #ifdef CONFIG_NAND_BOOT
 292 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 293 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 294 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 295 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 296 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 297 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 298 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 299 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 300 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 301 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 302 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 303 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 304 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 305 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 306 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 307 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 308 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 309 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 310 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 311 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 312 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 313 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 314 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 315 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 316 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 317 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 318 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 319 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 320 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 321 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 322 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 323 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 324 #else
 325 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 326 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 327 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 328 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 329 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 330 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 331 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 332 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 333 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 334 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 335 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 336 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 337 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 338 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 339 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 340 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 341 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 342 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 343 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 344 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 345 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 346 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 347 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 348 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 349 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 350 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 351 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 352 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 353 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 354 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 355 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 356 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 357 #endif
 358 #endif
 359
 360 /*
 361  * I2C bus multiplexer
 362  */
 363 #define I2C_MUX_PCA_ADDR_PRI            0x77
 364 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 365 #define I2C_RETIMER_ADDR                0x18
 366 #define I2C_MUX_CH_DEFAULT              0x8
 367 #define I2C_MUX_CH_CH7301               0xC
 368 #define I2C_MUX_CH5                     0xD
 369 #define I2C_MUX_CH6                     0xE
 370 #define I2C_MUX_CH7                     0xF
 371
 372 #define I2C_MUX_CH_VOL_MONITOR 0xa
 373
 374 /* Voltage monitor on channel 2*/
 375 #define I2C_VOL_MONITOR_ADDR           0x40
 376 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 377 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 378 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 379
 380 #define CONFIG_VID_FLS_ENV              "ls1046aqds_vdd_mv"
 381 #ifndef CONFIG_SPL_BUILD
 382 #define CONFIG_VID
 383 #endif
 384 #define CONFIG_VOL_MONITOR_IR36021_SET
 385 #define CONFIG_VOL_MONITOR_INA220
 386 /* The lowest and highest voltage allowed for LS1046AQDS */
 387 #define VDD_MV_MIN                      819
 388 #define VDD_MV_MAX                      1212
 389
 390 /*
 391  * Miscellaneous configurable options
 392  */
 393
 394 #define CONFIG_SYS_HZ                   1000
 395
 396 #define CONFIG_SYS_INIT_SP_OFFSET \
 397         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 398
 399 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 400
 401 /*
 402  * Environment
 403  */
 404
 405 #define CONFIG_CMDLINE_TAG
 406
 407 #undef CONFIG_BOOTCOMMAND
 408 #ifdef CONFIG_TFABOOT
 409 #define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; "   \
 410                            "env exists secureboot && esbc_halt;;"
 411 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd"      \
 412                            "env exists secureboot && esbc_halt;;"
 413 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "     \
 414                            "env exists secureboot && esbc_halt;;"
 415 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "   \
 416                            "env exists secureboot && esbc_halt;;"
 417 #else
 418 #if defined(CONFIG_QSPI_BOOT)
 419 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "      \
 420                            "env exists secureboot && esbc_halt;;"
 421 #elif defined(CONFIG_NAND_BOOT)
 422 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; "     \
 423                            "env exists secureboot && esbc_halt;;"
 424 #elif defined(CONFIG_SD_BOOT)
 425 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "       \
 426                            "env exists secureboot && esbc_halt;;"
 427 #else
 428 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "      \
 429                            "env exists secureboot && esbc_halt;;"
 430 #endif
 431 #endif
 432
 433 #include <asm/fsl_secure_boot.h>
 434
 435 #endif /* __LS1046AQDS_H__ */