Merge git://git.denx.de/u-boot-mpc85xx
[platform/kernel/u-boot.git] / include / configs / ls1046aqds.h
1 /*
2  * Copyright 2016 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #ifndef __LS1046AQDS_H__
8 #define __LS1046AQDS_H__
9
10 #include "ls1046a_common.h"
11
12 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
13 #define CONFIG_SYS_TEXT_BASE            0x82000000
14 #elif defined(CONFIG_QSPI_BOOT)
15 #define CONFIG_SYS_TEXT_BASE            0x40010000
16 #else
17 #define CONFIG_SYS_TEXT_BASE            0x60100000
18 #endif
19
20 #ifndef __ASSEMBLY__
21 unsigned long get_board_sys_clk(void);
22 unsigned long get_board_ddr_clk(void);
23 #endif
24
25 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
26 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
27
28 #define CONFIG_SKIP_LOWLEVEL_INIT
29
30 #define CONFIG_LAYERSCAPE_NS_ACCESS
31
32 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
33 /* Physical Memory Map */
34 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
35 #define CONFIG_NR_DRAM_BANKS            2
36
37 #define CONFIG_DDR_SPD
38 #define SPD_EEPROM_ADDRESS              0x51
39 #define CONFIG_SYS_SPD_BUS_NUM          0
40
41 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
42
43 #define CONFIG_DDR_ECC
44 #ifdef CONFIG_DDR_ECC
45 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
46 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
47 #endif
48
49 /* DSPI */
50 #ifdef CONFIG_FSL_DSPI
51 #define CONFIG_SPI_FLASH_STMICRO        /* cs0 */
52 #define CONFIG_SPI_FLASH_SST            /* cs1 */
53 #define CONFIG_SPI_FLASH_EON            /* cs2 */
54 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
55 #define CONFIG_SF_DEFAULT_BUS           1
56 #define CONFIG_SF_DEFAULT_CS            0
57 #endif
58 #endif
59
60 /* QSPI */
61 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
62 #ifdef CONFIG_FSL_QSPI
63 #define CONFIG_SPI_FLASH_SPANSION
64 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
65 #define FSL_QSPI_FLASH_NUM              2
66 #endif
67 #endif
68
69 #ifdef CONFIG_SYS_DPAA_FMAN
70 #define CONFIG_FMAN_ENET
71 #define CONFIG_PHYLIB
72 #define CONFIG_PHY_VITESSE
73 #define CONFIG_PHY_REALTEK
74 #define CONFIG_PHYLIB_10G
75 #define RGMII_PHY1_ADDR         0x1
76 #define RGMII_PHY2_ADDR         0x2
77 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
78 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
79 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
80 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
81 /* PHY address on QSGMII riser card on slot 2 */
82 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
83 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
84 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
85 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
86 #endif
87
88 #ifdef CONFIG_RAMBOOT_PBL
89 #define CONFIG_SYS_FSL_PBL_PBI \
90         board/freescale/ls1046aqds/ls1046aqds_pbi.cfg
91 #endif
92
93 #ifdef CONFIG_NAND_BOOT
94 #define CONFIG_SYS_FSL_PBL_RCW \
95         board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg
96 #endif
97
98 #ifdef CONFIG_SD_BOOT
99 #ifdef CONFIG_SD_BOOT_QSPI
100 #define CONFIG_SYS_FSL_PBL_RCW \
101         board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg
102 #else
103 #define CONFIG_SYS_FSL_PBL_RCW \
104         board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg
105 #endif
106 #endif
107
108 /* IFC */
109 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
110 #define CONFIG_FSL_IFC
111 /*
112  * CONFIG_SYS_FLASH_BASE has the final address (core view)
113  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
114  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
115  * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
116  */
117 #define CONFIG_SYS_FLASH_BASE                   0x60000000
118 #define CONFIG_SYS_FLASH_BASE_PHYS              CONFIG_SYS_FLASH_BASE
119 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY        0x00000000
120
121 #ifndef CONFIG_SYS_NO_FLASH
122 #define CONFIG_FLASH_CFI_DRIVER
123 #define CONFIG_SYS_FLASH_CFI
124 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
125 #define CONFIG_SYS_FLASH_QUIET_TEST
126 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
127 #endif
128 #endif
129
130 /* LPUART */
131 #ifdef CONFIG_LPUART
132 #define CONFIG_LPUART_32B_REG
133 #define CFG_UART_MUX_MASK       0x6
134 #define CFG_UART_MUX_SHIFT      1
135 #define CFG_LPUART_EN           0x2
136 #endif
137
138 /* SATA */
139 #define CONFIG_LIBATA
140 #define CONFIG_SCSI_AHCI
141 #define CONFIG_SCSI_AHCI_PLAT
142 #define CONFIG_SCSI
143
144 /* EEPROM */
145 #define CONFIG_ID_EEPROM
146 #define CONFIG_SYS_I2C_EEPROM_NXID
147 #define CONFIG_SYS_EEPROM_BUS_NUM               0
148 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x57
149 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
150 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
151 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
152
153 #define CONFIG_SYS_SATA                         AHCI_BASE_ADDR
154
155 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
156 #define CONFIG_SYS_SCSI_MAX_LUN                 1
157 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
158                                                 CONFIG_SYS_SCSI_MAX_LUN)
159
160 /*
161  * IFC Definitions
162  */
163 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
164 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
165 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
166                                 CSPR_PORT_SIZE_16 | \
167                                 CSPR_MSEL_NOR | \
168                                 CSPR_V)
169 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
170 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
171                                 + 0x8000000) | \
172                                 CSPR_PORT_SIZE_16 | \
173                                 CSPR_MSEL_NOR | \
174                                 CSPR_V)
175 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
176
177 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
178                                         CSOR_NOR_TRHZ_80)
179 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
180                                         FTIM0_NOR_TEADC(0x5) | \
181                                         FTIM0_NOR_TEAHC(0x5))
182 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
183                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
184                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
185 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
186                                         FTIM2_NOR_TCH(0x4) | \
187                                         FTIM2_NOR_TWPH(0xe) | \
188                                         FTIM2_NOR_TWP(0x1c))
189 #define CONFIG_SYS_NOR_FTIM3            0
190
191 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
192 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
193 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
194 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
195
196 #define CONFIG_SYS_FLASH_EMPTY_INFO
197 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
198                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
199
200 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
201 #define CONFIG_SYS_WRITE_SWAPPED_DATA
202
203 /*
204  * NAND Flash Definitions
205  */
206 #define CONFIG_NAND_FSL_IFC
207
208 #define CONFIG_SYS_NAND_BASE            0x7e800000
209 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
210
211 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
212
213 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
214                                 | CSPR_PORT_SIZE_8      \
215                                 | CSPR_MSEL_NAND        \
216                                 | CSPR_V)
217 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
218 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
219                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
220                                 | CSOR_NAND_ECC_MODE_8  /* 8-bit ECC */ \
221                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
222                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
223                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
224                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
225
226 #define CONFIG_SYS_NAND_ONFI_DETECTION
227
228 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
229                                         FTIM0_NAND_TWP(0x18)   | \
230                                         FTIM0_NAND_TWCHT(0x7) | \
231                                         FTIM0_NAND_TWH(0xa))
232 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
233                                         FTIM1_NAND_TWBE(0x39)  | \
234                                         FTIM1_NAND_TRR(0xe)   | \
235                                         FTIM1_NAND_TRP(0x18))
236 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
237                                         FTIM2_NAND_TREH(0xa) | \
238                                         FTIM2_NAND_TWHRE(0x1e))
239 #define CONFIG_SYS_NAND_FTIM3           0x0
240
241 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
242 #define CONFIG_SYS_MAX_NAND_DEVICE      1
243 #define CONFIG_MTD_NAND_VERIFY_WRITE
244 #define CONFIG_CMD_NAND
245
246 #define CONFIG_SYS_NAND_BLOCK_SIZE      (256 * 1024)
247 #endif
248
249 #ifdef CONFIG_NAND_BOOT
250 #define CONFIG_SPL_PAD_TO               0x40000         /* block aligned */
251 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
252 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
253 #endif
254
255 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
256 #define CONFIG_QIXIS_I2C_ACCESS
257 #define CONFIG_SYS_I2C_EARLY_INIT
258 #define CONFIG_SYS_NO_FLASH
259 #endif
260
261 /*
262  * QIXIS Definitions
263  */
264 #define CONFIG_FSL_QIXIS
265
266 #ifdef CONFIG_FSL_QIXIS
267 #define QIXIS_BASE                      0x7fb00000
268 #define QIXIS_BASE_PHYS                 QIXIS_BASE
269 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
270 #define QIXIS_LBMAP_SWITCH              6
271 #define QIXIS_LBMAP_MASK                0x0f
272 #define QIXIS_LBMAP_SHIFT               0
273 #define QIXIS_LBMAP_DFLTBANK            0x00
274 #define QIXIS_LBMAP_ALTBANK             0x04
275 #define QIXIS_LBMAP_NAND                0x09
276 #define QIXIS_LBMAP_SD                  0x00
277 #define QIXIS_LBMAP_SD_QSPI             0xff
278 #define QIXIS_LBMAP_QSPI                0xff
279 #define QIXIS_RCW_SRC_NAND              0x110
280 #define QIXIS_RCW_SRC_SD                0x040
281 #define QIXIS_RCW_SRC_QSPI              0x045
282 #define QIXIS_RST_CTL_RESET             0x41
283 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
284 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
285 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
286
287 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
288 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
289                                         CSPR_PORT_SIZE_8 | \
290                                         CSPR_MSEL_GPCM | \
291                                         CSPR_V)
292 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
293 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
294                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
295                                         CSOR_NOR_TRHZ_80)
296
297 /*
298  * QIXIS Timing parameters for IFC GPCM
299  */
300 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xc) | \
301                                         FTIM0_GPCM_TEADC(0x20) | \
302                                         FTIM0_GPCM_TEAHC(0x10))
303 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0x50) | \
304                                         FTIM1_GPCM_TRAD(0x1f))
305 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0x8) | \
306                                         FTIM2_GPCM_TCH(0x8) | \
307                                         FTIM2_GPCM_TWP(0xf0))
308 #define CONFIG_SYS_FPGA_FTIM3           0x0
309 #endif
310
311 #ifdef CONFIG_NAND_BOOT
312 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
313 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
314 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
315 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
316 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
317 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
318 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
319 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
320 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
321 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
322 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
323 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
324 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
325 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
326 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
327 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
328 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
329 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
330 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
331 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
332 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
333 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
334 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
335 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
336 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
337 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
338 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
339 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
340 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
341 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
342 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
343 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
344 #else
345 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
346 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
347 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
348 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
349 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
350 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
351 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
352 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
353 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
354 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
355 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
356 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
357 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
358 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
359 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
360 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
361 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
362 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
363 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
364 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
365 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
366 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
367 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
368 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
369 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
370 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
371 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
372 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
373 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
374 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
375 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
376 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
377 #endif
378
379 /*
380  * I2C bus multiplexer
381  */
382 #define I2C_MUX_PCA_ADDR_PRI            0x77
383 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
384 #define I2C_RETIMER_ADDR                0x18
385 #define I2C_MUX_CH_DEFAULT              0x8
386 #define I2C_MUX_CH_CH7301               0xC
387 #define I2C_MUX_CH5                     0xD
388 #define I2C_MUX_CH6                     0xE
389 #define I2C_MUX_CH7                     0xF
390
391 #define I2C_MUX_CH_VOL_MONITOR 0xa
392
393 /* Voltage monitor on channel 2*/
394 #define I2C_VOL_MONITOR_ADDR           0x40
395 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
396 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
397 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
398
399 #define CONFIG_VID_FLS_ENV              "ls1046aqds_vdd_mv"
400 #ifndef CONFIG_SPL_BUILD
401 #define CONFIG_VID
402 #endif
403 #define CONFIG_VOL_MONITOR_IR36021_SET
404 #define CONFIG_VOL_MONITOR_INA220
405 /* The lowest and highest voltage allowed for LS1046AQDS */
406 #define VDD_MV_MIN                      819
407 #define VDD_MV_MAX                      1212
408
409 /*
410  * Miscellaneous configurable options
411  */
412 #define CONFIG_MISC_INIT_R
413 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
414 #define CONFIG_AUTO_COMPLETE
415 #define CONFIG_SYS_PBSIZE               \
416                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
417 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
418
419 #define CONFIG_SYS_MEMTEST_START        0x80000000
420 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
421
422 #define CONFIG_SYS_HZ                   1000
423
424 /*
425  * Stack sizes
426  * The stack sizes are set up in start.S using the settings below
427  */
428 #define CONFIG_STACKSIZE                (30 * 1024)
429
430 #define CONFIG_SYS_INIT_SP_OFFSET \
431         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
432
433 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
434
435 /*
436  * Environment
437  */
438 #define CONFIG_ENV_OVERWRITE
439
440 #ifdef CONFIG_NAND_BOOT
441 #define CONFIG_ENV_IS_IN_NAND
442 #define CONFIG_ENV_SIZE                 0x2000
443 #define CONFIG_ENV_OFFSET               (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
444 #elif defined(CONFIG_SD_BOOT)
445 #define CONFIG_ENV_OFFSET               (1024 * 1024)
446 #define CONFIG_ENV_IS_IN_MMC
447 #define CONFIG_SYS_MMC_ENV_DEV          0
448 #define CONFIG_ENV_SIZE                 0x2000
449 #elif defined(CONFIG_QSPI_BOOT)
450 #define CONFIG_ENV_IS_IN_SPI_FLASH
451 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
452 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
453 #define CONFIG_ENV_SECT_SIZE            0x10000
454 #else
455 #define CONFIG_ENV_IS_IN_FLASH
456 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x200000)
457 #define CONFIG_ENV_SECT_SIZE            0x20000
458 #define CONFIG_ENV_SIZE                 0x20000
459 #endif
460
461 #define CONFIG_CMDLINE_TAG
462
463 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
464 #define CONFIG_BOOTCOMMAND              "sf probe && sf read $kernel_load "    \
465                                         "e0000 f00000 && bootm $kernel_load"
466 #else
467 #define CONFIG_BOOTCOMMAND              "cp.b $kernel_start $kernel_load "     \
468                                         "$kernel_size && bootm $kernel_load"
469 #endif
470
471 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
472 #define MTDPARTS_DEFAULT "mtdparts=1550000.quadspi:2m(uboot)," \
473                         "14m(free)"
474 #else
475 #define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \
476                         "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \
477                         "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \
478                         "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \
479                         "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \
480                         "40m(nor_bank4_fit);7e800000.flash:" \
481                         "4m(nand_uboot),36m(nand_kernel)," \
482                         "472m(nand_free);spi0.0:2m(uboot)," \
483                         "14m(free)"
484 #endif
485
486 #include <asm/fsl_secure_boot.h>
487
488 #endif /* __LS1046AQDS_H__ */