include/configs/ls1046aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __LS1046AQDS_H__
   7 #define __LS1046AQDS_H__
   8
   9 #include "ls1046a_common.h"
  10
  11 #ifndef __ASSEMBLY__
  12 unsigned long get_board_sys_clk(void);
  13 unsigned long get_board_ddr_clk(void);
  14 #endif
  15
  16 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  17 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
  18
  19 #define CONFIG_SKIP_LOWLEVEL_INIT
  20
  21 #define CONFIG_LAYERSCAPE_NS_ACCESS
  22
  23 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  24 /* Physical Memory Map */
  25 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  26
  27 #define CONFIG_DDR_SPD
  28 #define SPD_EEPROM_ADDRESS              0x51
  29 #define CONFIG_SYS_SPD_BUS_NUM          0
  30
  31 #define CONFIG_DDR_ECC
  32 #ifdef CONFIG_DDR_ECC
  33 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  34 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  35 #endif
  36
  37 /* DSPI */
  38 #ifdef CONFIG_FSL_DSPI
  39 #define CONFIG_SPI_FLASH_STMICRO        /* cs0 */
  40 #define CONFIG_SPI_FLASH_SST            /* cs1 */
  41 #define CONFIG_SPI_FLASH_EON            /* cs2 */
  42 #endif
  43
  44 /* QSPI */
  45 #if defined(CONFIG_TFABOOT) ||  \
  46         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  47 #ifdef CONFIG_FSL_QSPI
  48 #define CONFIG_SPI_FLASH_SPANSION
  49 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
  50 #define FSL_QSPI_FLASH_NUM              2
  51 #endif
  52 #endif
  53
  54 #ifdef CONFIG_SYS_DPAA_FMAN
  55 #define CONFIG_PHY_VITESSE
  56 #define CONFIG_PHY_REALTEK
  57 #define CONFIG_PHYLIB_10G
  58 #define RGMII_PHY1_ADDR         0x1
  59 #define RGMII_PHY2_ADDR         0x2
  60 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  61 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  62 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  63 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  64 /* PHY address on QSGMII riser card on slot 2 */
  65 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
  66 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
  67 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
  68 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
  69 #endif
  70
  71 #ifdef CONFIG_RAMBOOT_PBL
  72 #define CONFIG_SYS_FSL_PBL_PBI \
  73         board/freescale/ls1046aqds/ls1046aqds_pbi.cfg
  74 #endif
  75
  76 #ifdef CONFIG_NAND_BOOT
  77 #define CONFIG_SYS_FSL_PBL_RCW \
  78         board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg
  79 #endif
  80
  81 #ifdef CONFIG_SD_BOOT
  82 #ifdef CONFIG_SD_BOOT_QSPI
  83 #define CONFIG_SYS_FSL_PBL_RCW \
  84         board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg
  85 #else
  86 #define CONFIG_SYS_FSL_PBL_RCW \
  87         board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg
  88 #endif
  89 #endif
  90
  91 /* IFC */
  92 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  93 #define CONFIG_FSL_IFC
  94 /*
  95  * CONFIG_SYS_FLASH_BASE has the final address (core view)
  96  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
  97  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  98  * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
  99  */
 100 #define CONFIG_SYS_FLASH_BASE                   0x60000000
 101 #define CONFIG_SYS_FLASH_BASE_PHYS              CONFIG_SYS_FLASH_BASE
 102 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY        0x00000000
 103
 104 #ifdef CONFIG_MTD_NOR_FLASH
 105 #define CONFIG_SYS_FLASH_QUIET_TEST
 106 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 107 #endif
 108 #endif
 109
 110 /* LPUART */
 111 #ifdef CONFIG_LPUART
 112 #define CONFIG_LPUART_32B_REG
 113 #define CFG_UART_MUX_MASK       0x6
 114 #define CFG_UART_MUX_SHIFT      1
 115 #define CFG_LPUART_EN           0x2
 116 #endif
 117
 118 /* EEPROM */
 119 #define CONFIG_ID_EEPROM
 120 #define CONFIG_SYS_I2C_EEPROM_NXID
 121 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 122 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x57
 123 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 124 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 125 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 126
 127 /*
 128  * IFC Definitions
 129  */
 130 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 131 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
 132 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 133                                 CSPR_PORT_SIZE_16 | \
 134                                 CSPR_MSEL_NOR | \
 135                                 CSPR_V)
 136 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
 137 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 138                                 + 0x8000000) | \
 139                                 CSPR_PORT_SIZE_16 | \
 140                                 CSPR_MSEL_NOR | \
 141                                 CSPR_V)
 142 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 143
 144 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 145                                         CSOR_NOR_TRHZ_80)
 146 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 147                                         FTIM0_NOR_TEADC(0x5) | \
 148                                         FTIM0_NOR_TAVDS(0x6) | \
 149                                         FTIM0_NOR_TEAHC(0x5))
 150 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 151                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
 152                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 153 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x8) | \
 154                                         FTIM2_NOR_TCH(0x8) | \
 155                                         FTIM2_NOR_TWPH(0xe) | \
 156                                         FTIM2_NOR_TWP(0x1c))
 157 #define CONFIG_SYS_NOR_FTIM3            0
 158
 159 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 160 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 161 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 162 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 163
 164 #define CONFIG_SYS_FLASH_EMPTY_INFO
 165 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 166                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 167
 168 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 169 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 170
 171 /*
 172  * NAND Flash Definitions
 173  */
 174 #define CONFIG_NAND_FSL_IFC
 175
 176 #define CONFIG_SYS_NAND_BASE            0x7e800000
 177 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 178
 179 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 180
 181 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 182                                 | CSPR_PORT_SIZE_8      \
 183                                 | CSPR_MSEL_NAND        \
 184                                 | CSPR_V)
 185 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 186 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 187                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 188                                 | CSOR_NAND_ECC_MODE_8  /* 8-bit ECC */ \
 189                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 190                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 191                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 192                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 193
 194 #define CONFIG_SYS_NAND_ONFI_DETECTION
 195
 196 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 197                                         FTIM0_NAND_TWP(0x18)   | \
 198                                         FTIM0_NAND_TWCHT(0x7) | \
 199                                         FTIM0_NAND_TWH(0xa))
 200 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 201                                         FTIM1_NAND_TWBE(0x39)  | \
 202                                         FTIM1_NAND_TRR(0xe)   | \
 203                                         FTIM1_NAND_TRP(0x18))
 204 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 205                                         FTIM2_NAND_TREH(0xa) | \
 206                                         FTIM2_NAND_TWHRE(0x1e))
 207 #define CONFIG_SYS_NAND_FTIM3           0x0
 208
 209 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 210 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 211 #define CONFIG_MTD_NAND_VERIFY_WRITE
 212
 213 #define CONFIG_SYS_NAND_BLOCK_SIZE      (256 * 1024)
 214 #endif
 215
 216 #ifdef CONFIG_NAND_BOOT
 217 #define CONFIG_SPL_PAD_TO               0x40000         /* block aligned */
 218 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
 219 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
 220 #endif
 221
 222 #if defined(CONFIG_TFABOOT) || \
 223         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 224 #define CONFIG_QIXIS_I2C_ACCESS
 225 #define CONFIG_SYS_I2C_EARLY_INIT
 226 #endif
 227
 228 /*
 229  * QIXIS Definitions
 230  */
 231 #define CONFIG_FSL_QIXIS
 232
 233 #ifdef CONFIG_FSL_QIXIS
 234 #define QIXIS_BASE                      0x7fb00000
 235 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 236 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 237 #define QIXIS_LBMAP_SWITCH              6
 238 #define QIXIS_LBMAP_MASK                0x0f
 239 #define QIXIS_LBMAP_SHIFT               0
 240 #define QIXIS_LBMAP_DFLTBANK            0x00
 241 #define QIXIS_LBMAP_ALTBANK             0x04
 242 #define QIXIS_LBMAP_NAND                0x09
 243 #define QIXIS_LBMAP_SD                  0x00
 244 #define QIXIS_LBMAP_SD_QSPI             0xff
 245 #define QIXIS_LBMAP_QSPI                0xff
 246 #define QIXIS_RCW_SRC_NAND              0x110
 247 #define QIXIS_RCW_SRC_SD                0x040
 248 #define QIXIS_RCW_SRC_QSPI              0x045
 249 #define QIXIS_RST_CTL_RESET             0x41
 250 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 251 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 252 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 253
 254 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 255 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 256                                         CSPR_PORT_SIZE_8 | \
 257                                         CSPR_MSEL_GPCM | \
 258                                         CSPR_V)
 259 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 260 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 261                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 262                                         CSOR_NOR_TRHZ_80)
 263
 264 /*
 265  * QIXIS Timing parameters for IFC GPCM
 266  */
 267 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xc) | \
 268                                         FTIM0_GPCM_TEADC(0x20) | \
 269                                         FTIM0_GPCM_TEAHC(0x10))
 270 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0x50) | \
 271                                         FTIM1_GPCM_TRAD(0x1f))
 272 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0x8) | \
 273                                         FTIM2_GPCM_TCH(0x8) | \
 274                                         FTIM2_GPCM_TWP(0xf0))
 275 #define CONFIG_SYS_FPGA_FTIM3           0x0
 276 #endif
 277
 278 #ifdef CONFIG_TFABOOT
 279 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 280 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 281 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 282 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 283 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 284 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 285 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 286 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 287 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 288 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 289 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 290 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 291 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 292 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 293 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 294 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 295 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 296 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 297 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 298 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 299 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 300 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 301 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 302 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 303 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 304 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 305 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 306 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 307 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 308 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 309 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 310 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 311 #else
 312 #ifdef CONFIG_NAND_BOOT
 313 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 314 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 315 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 316 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 317 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 318 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 319 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 320 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 321 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 322 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 323 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 324 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 325 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 326 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 327 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 328 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 329 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 330 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 331 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 332 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 333 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 334 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 335 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 336 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 337 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 338 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 339 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 340 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 341 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 342 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 343 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 344 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 345 #else
 346 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 347 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 348 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 349 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 350 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 351 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 352 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 353 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 354 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 355 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 356 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 357 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 358 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 359 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 360 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 361 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 362 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 363 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 364 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 365 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 366 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 367 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 368 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 369 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 370 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 371 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 372 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 373 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 374 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 375 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 376 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 377 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 378 #endif
 379 #endif
 380
 381 /*
 382  * I2C bus multiplexer
 383  */
 384 #define I2C_MUX_PCA_ADDR_PRI            0x77
 385 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 386 #define I2C_RETIMER_ADDR                0x18
 387 #define I2C_MUX_CH_DEFAULT              0x8
 388 #define I2C_MUX_CH_CH7301               0xC
 389 #define I2C_MUX_CH5                     0xD
 390 #define I2C_MUX_CH6                     0xE
 391 #define I2C_MUX_CH7                     0xF
 392
 393 #define I2C_MUX_CH_VOL_MONITOR 0xa
 394
 395 /* Voltage monitor on channel 2*/
 396 #define I2C_VOL_MONITOR_ADDR           0x40
 397 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 398 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 399 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 400
 401 #define CONFIG_VID_FLS_ENV              "ls1046aqds_vdd_mv"
 402 #ifndef CONFIG_SPL_BUILD
 403 #define CONFIG_VID
 404 #endif
 405 #define CONFIG_VOL_MONITOR_IR36021_SET
 406 #define CONFIG_VOL_MONITOR_INA220
 407 /* The lowest and highest voltage allowed for LS1046AQDS */
 408 #define VDD_MV_MIN                      819
 409 #define VDD_MV_MAX                      1212
 410
 411 /*
 412  * Miscellaneous configurable options
 413  */
 414
 415 #define CONFIG_SYS_MEMTEST_START        0x80000000
 416 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
 417
 418 #define CONFIG_SYS_HZ                   1000
 419
 420 #define CONFIG_SYS_INIT_SP_OFFSET \
 421         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 422
 423 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 424
 425 /*
 426  * Environment
 427  */
 428 #define CONFIG_ENV_OVERWRITE
 429
 430 #ifdef CONFIG_TFABOOT
 431 #define CONFIG_SYS_MMC_ENV_DEV          0
 432
 433 #define CONFIG_ENV_SIZE                 0x2000
 434 #define CONFIG_ENV_OFFSET               0x500000        /* 5MB */
 435 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x500000)
 436 #define CONFIG_ENV_SECT_SIZE            0x20000
 437 #else
 438 #ifdef CONFIG_NAND_BOOT
 439 #define CONFIG_ENV_SIZE                 0x2000
 440 #define CONFIG_ENV_OFFSET               (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 441 #elif defined(CONFIG_SD_BOOT)
 442 #define CONFIG_ENV_OFFSET               (3 * 1024 * 1024)
 443 #define CONFIG_SYS_MMC_ENV_DEV          0
 444 #define CONFIG_ENV_SIZE                 0x2000
 445 #elif defined(CONFIG_QSPI_BOOT)
 446 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 447 #define CONFIG_ENV_OFFSET               0x300000        /* 3MB */
 448 #define CONFIG_ENV_SECT_SIZE            0x10000
 449 #else
 450 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x300000)
 451 #define CONFIG_ENV_SECT_SIZE            0x20000
 452 #define CONFIG_ENV_SIZE                 0x20000
 453 #endif
 454 #endif
 455
 456 #define CONFIG_CMDLINE_TAG
 457
 458 #undef CONFIG_BOOTCOMMAND
 459 #ifdef CONFIG_TFABOOT
 460 #define QSPI_NOR_BOOTCOMMAND            "sf probe && sf read $kernel_load "    \
 461                                         "e0000 f00000 && bootm $kernel_load"
 462 #define IFC_NOR_BOOTCOMMAND             "cp.b $kernel_start $kernel_load "     \
 463                                         "$kernel_size && bootm $kernel_load"
 464 #define SD_BOOTCOMMAND          "mmc info; mmc read $kernel_load"     \
 465                                         "$kernel_addr_sd $kernel_size_sd && bootm $kernel_load"
 466 #else
 467 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 468 #define CONFIG_BOOTCOMMAND              "sf probe && sf read $kernel_load "    \
 469                                         "e0000 f00000 && bootm $kernel_load"
 470 #else
 471 #define CONFIG_BOOTCOMMAND              "cp.b $kernel_start $kernel_load "     \
 472                                         "$kernel_size && bootm $kernel_load"
 473 #endif
 474 #endif
 475
 476 #include <asm/fsl_secure_boot.h>
 477
 478 #endif /* __LS1046AQDS_H__ */