include/configs/ls1046aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __LS1046AQDS_H__
   7 #define __LS1046AQDS_H__
   8
   9 #include "ls1046a_common.h"
  10
  11 /* Physical Memory Map */
  12
  13 #define SPD_EEPROM_ADDRESS              0x51
  14
  15 #ifdef CONFIG_DDR_ECC
  16 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  17 #endif
  18
  19 #ifdef CONFIG_SYS_DPAA_FMAN
  20 #define RGMII_PHY1_ADDR         0x1
  21 #define RGMII_PHY2_ADDR         0x2
  22 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  23 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  24 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  25 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  26 /* PHY address on QSGMII riser card on slot 2 */
  27 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
  28 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
  29 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
  30 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
  31 #endif
  32
  33 /* IFC */
  34 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  35 /*
  36  * CFG_SYS_FLASH_BASE has the final address (core view)
  37  * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
  38  * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  39  * CONFIG_TEXT_BASE is linked to 0x60000000 for booting
  40  */
  41 #define CFG_SYS_FLASH_BASE                      0x60000000
  42 #define CFG_SYS_FLASH_BASE_PHYS         CFG_SYS_FLASH_BASE
  43 #define CFG_SYS_FLASH_BASE_PHYS_EARLY   0x00000000
  44 #endif
  45
  46 /* LPUART */
  47 #ifdef CONFIG_LPUART
  48 #define CFG_UART_MUX_MASK       0x6
  49 #define CFG_UART_MUX_SHIFT      1
  50 #define CFG_LPUART_EN           0x2
  51 #endif
  52
  53 /*
  54  * IFC Definitions
  55  */
  56 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  57 #define CFG_SYS_NOR0_CSPR_EXT   (0x0)
  58 #define CFG_SYS_NOR0_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
  59                                 CSPR_PORT_SIZE_16 | \
  60                                 CSPR_MSEL_NOR | \
  61                                 CSPR_V)
  62 #define CFG_SYS_NOR1_CSPR_EXT   (0x0)
  63 #define CFG_SYS_NOR1_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \
  64                                 + 0x8000000) | \
  65                                 CSPR_PORT_SIZE_16 | \
  66                                 CSPR_MSEL_NOR | \
  67                                 CSPR_V)
  68 #define CFG_SYS_NOR_AMASK               IFC_AMASK(128 * 1024 * 1024)
  69
  70 #define CFG_SYS_NOR_CSOR                (CSOR_NOR_ADM_SHIFT(4) | \
  71                                         CSOR_NOR_TRHZ_80)
  72 #define CFG_SYS_NOR_FTIM0               (FTIM0_NOR_TACSE(0x4) | \
  73                                         FTIM0_NOR_TEADC(0x5) | \
  74                                         FTIM0_NOR_TAVDS(0x6) | \
  75                                         FTIM0_NOR_TEAHC(0x5))
  76 #define CFG_SYS_NOR_FTIM1               (FTIM1_NOR_TACO(0x35) | \
  77                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
  78                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
  79 #define CFG_SYS_NOR_FTIM2               (FTIM2_NOR_TCS(0x8) | \
  80                                         FTIM2_NOR_TCH(0x8) | \
  81                                         FTIM2_NOR_TWPH(0xe) | \
  82                                         FTIM2_NOR_TWP(0x1c))
  83 #define CFG_SYS_NOR_FTIM3               0
  84
  85 #define CFG_SYS_FLASH_BANKS_LIST        {CFG_SYS_FLASH_BASE_PHYS, \
  86                                         CFG_SYS_FLASH_BASE_PHYS + 0x8000000}
  87
  88 #define CFG_SYS_WRITE_SWAPPED_DATA
  89
  90 /*
  91  * NAND Flash Definitions
  92  */
  93
  94 #define CFG_SYS_NAND_BASE               0x7e800000
  95 #define CFG_SYS_NAND_BASE_PHYS  CFG_SYS_NAND_BASE
  96
  97 #define CFG_SYS_NAND_CSPR_EXT   (0x0)
  98
  99 #define CFG_SYS_NAND_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 100                                 | CSPR_PORT_SIZE_8      \
 101                                 | CSPR_MSEL_NAND        \
 102                                 | CSPR_V)
 103 #define CFG_SYS_NAND_AMASK      IFC_AMASK(64*1024)
 104 #define CFG_SYS_NAND_CSOR       (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 105                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 106                                 | CSOR_NAND_ECC_MODE_8  /* 8-bit ECC */ \
 107                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 108                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 109                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 110                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 111
 112 #define CFG_SYS_NAND_FTIM0              (FTIM0_NAND_TCCST(0x7) | \
 113                                         FTIM0_NAND_TWP(0x18)   | \
 114                                         FTIM0_NAND_TWCHT(0x7) | \
 115                                         FTIM0_NAND_TWH(0xa))
 116 #define CFG_SYS_NAND_FTIM1              (FTIM1_NAND_TADLE(0x32) | \
 117                                         FTIM1_NAND_TWBE(0x39)  | \
 118                                         FTIM1_NAND_TRR(0xe)   | \
 119                                         FTIM1_NAND_TRP(0x18))
 120 #define CFG_SYS_NAND_FTIM2              (FTIM2_NAND_TRAD(0xf) | \
 121                                         FTIM2_NAND_TREH(0xa) | \
 122                                         FTIM2_NAND_TWHRE(0x1e))
 123 #define CFG_SYS_NAND_FTIM3           0x0
 124
 125 #define CFG_SYS_NAND_BASE_LIST  { CFG_SYS_NAND_BASE }
 126 #endif
 127
 128 #ifdef CONFIG_NAND_BOOT
 129 #define CFG_SYS_NAND_U_BOOT_SIZE        (768 << 10)
 130 #endif
 131
 132 #if defined(CONFIG_TFABOOT) || \
 133         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 134 #endif
 135
 136 /*
 137  * QIXIS Definitions
 138  */
 139
 140 #ifdef CONFIG_FSL_QIXIS
 141 #define QIXIS_BASE                      0x7fb00000
 142 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 143 #define CFG_SYS_I2C_FPGA_ADDR   0x66
 144 #define QIXIS_LBMAP_SWITCH              6
 145 #define QIXIS_LBMAP_MASK                0x0f
 146 #define QIXIS_LBMAP_SHIFT               0
 147 #define QIXIS_LBMAP_DFLTBANK            0x00
 148 #define QIXIS_LBMAP_ALTBANK             0x04
 149 #define QIXIS_LBMAP_NAND                0x09
 150 #define QIXIS_LBMAP_SD                  0x00
 151 #define QIXIS_LBMAP_SD_QSPI             0xff
 152 #define QIXIS_LBMAP_QSPI                0xff
 153 #define QIXIS_RCW_SRC_NAND              0x110
 154 #define QIXIS_RCW_SRC_SD                0x040
 155 #define QIXIS_RCW_SRC_QSPI              0x045
 156 #define QIXIS_RST_CTL_RESET             0x41
 157 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 158 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 159 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 160
 161 #define CFG_SYS_FPGA_CSPR_EXT   (0x0)
 162 #define CFG_SYS_FPGA_CSPR               (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 163                                         CSPR_PORT_SIZE_8 | \
 164                                         CSPR_MSEL_GPCM | \
 165                                         CSPR_V)
 166 #define CFG_SYS_FPGA_AMASK              IFC_AMASK(64 * 1024)
 167 #define CFG_SYS_FPGA_CSOR               (CSOR_NOR_ADM_SHIFT(4) | \
 168                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 169                                         CSOR_NOR_TRHZ_80)
 170
 171 /*
 172  * QIXIS Timing parameters for IFC GPCM
 173  */
 174 #define CFG_SYS_FPGA_FTIM0              (FTIM0_GPCM_TACSE(0xc) | \
 175                                         FTIM0_GPCM_TEADC(0x20) | \
 176                                         FTIM0_GPCM_TEAHC(0x10))
 177 #define CFG_SYS_FPGA_FTIM1              (FTIM1_GPCM_TACO(0x50) | \
 178                                         FTIM1_GPCM_TRAD(0x1f))
 179 #define CFG_SYS_FPGA_FTIM2              (FTIM2_GPCM_TCS(0x8) | \
 180                                         FTIM2_GPCM_TCH(0x8) | \
 181                                         FTIM2_GPCM_TWP(0xf0))
 182 #define CFG_SYS_FPGA_FTIM3              0x0
 183 #endif
 184
 185 #ifdef CONFIG_TFABOOT
 186 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NOR0_CSPR_EXT
 187 #define CFG_SYS_CSPR0           CFG_SYS_NOR0_CSPR
 188 #define CFG_SYS_AMASK0          CFG_SYS_NOR_AMASK
 189 #define CFG_SYS_CSOR0           CFG_SYS_NOR_CSOR
 190 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NOR_FTIM0
 191 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NOR_FTIM1
 192 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NOR_FTIM2
 193 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NOR_FTIM3
 194 #define CFG_SYS_CSPR1_EXT               CFG_SYS_NOR1_CSPR_EXT
 195 #define CFG_SYS_CSPR1           CFG_SYS_NOR1_CSPR
 196 #define CFG_SYS_AMASK1          CFG_SYS_NOR_AMASK
 197 #define CFG_SYS_CSOR1           CFG_SYS_NOR_CSOR
 198 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NOR_FTIM0
 199 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NOR_FTIM1
 200 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NOR_FTIM2
 201 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NOR_FTIM3
 202 #define CFG_SYS_CSPR2_EXT               CFG_SYS_NAND_CSPR_EXT
 203 #define CFG_SYS_CSPR2           CFG_SYS_NAND_CSPR
 204 #define CFG_SYS_AMASK2          CFG_SYS_NAND_AMASK
 205 #define CFG_SYS_CSOR2           CFG_SYS_NAND_CSOR
 206 #define CFG_SYS_CS2_FTIM0               CFG_SYS_NAND_FTIM0
 207 #define CFG_SYS_CS2_FTIM1               CFG_SYS_NAND_FTIM1
 208 #define CFG_SYS_CS2_FTIM2               CFG_SYS_NAND_FTIM2
 209 #define CFG_SYS_CS2_FTIM3               CFG_SYS_NAND_FTIM3
 210 #define CFG_SYS_CSPR3_EXT               CFG_SYS_FPGA_CSPR_EXT
 211 #define CFG_SYS_CSPR3           CFG_SYS_FPGA_CSPR
 212 #define CFG_SYS_AMASK3          CFG_SYS_FPGA_AMASK
 213 #define CFG_SYS_CSOR3           CFG_SYS_FPGA_CSOR
 214 #define CFG_SYS_CS3_FTIM0               CFG_SYS_FPGA_FTIM0
 215 #define CFG_SYS_CS3_FTIM1               CFG_SYS_FPGA_FTIM1
 216 #define CFG_SYS_CS3_FTIM2               CFG_SYS_FPGA_FTIM2
 217 #define CFG_SYS_CS3_FTIM3               CFG_SYS_FPGA_FTIM3
 218 #else
 219 #ifdef CONFIG_NAND_BOOT
 220 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NAND_CSPR_EXT
 221 #define CFG_SYS_CSPR0           CFG_SYS_NAND_CSPR
 222 #define CFG_SYS_AMASK0          CFG_SYS_NAND_AMASK
 223 #define CFG_SYS_CSOR0           CFG_SYS_NAND_CSOR
 224 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NAND_FTIM0
 225 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NAND_FTIM1
 226 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NAND_FTIM2
 227 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NAND_FTIM3
 228 #define CFG_SYS_CSPR1_EXT               CFG_SYS_NOR0_CSPR_EXT
 229 #define CFG_SYS_CSPR1           CFG_SYS_NOR0_CSPR
 230 #define CFG_SYS_AMASK1          CFG_SYS_NOR_AMASK
 231 #define CFG_SYS_CSOR1           CFG_SYS_NOR_CSOR
 232 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NOR_FTIM0
 233 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NOR_FTIM1
 234 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NOR_FTIM2
 235 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NOR_FTIM3
 236 #define CFG_SYS_CSPR2_EXT               CFG_SYS_NOR1_CSPR_EXT
 237 #define CFG_SYS_CSPR2           CFG_SYS_NOR1_CSPR
 238 #define CFG_SYS_AMASK2          CFG_SYS_NOR_AMASK
 239 #define CFG_SYS_CSOR2           CFG_SYS_NOR_CSOR
 240 #define CFG_SYS_CS2_FTIM0               CFG_SYS_NOR_FTIM0
 241 #define CFG_SYS_CS2_FTIM1               CFG_SYS_NOR_FTIM1
 242 #define CFG_SYS_CS2_FTIM2               CFG_SYS_NOR_FTIM2
 243 #define CFG_SYS_CS2_FTIM3               CFG_SYS_NOR_FTIM3
 244 #define CFG_SYS_CSPR3_EXT               CFG_SYS_FPGA_CSPR_EXT
 245 #define CFG_SYS_CSPR3           CFG_SYS_FPGA_CSPR
 246 #define CFG_SYS_AMASK3          CFG_SYS_FPGA_AMASK
 247 #define CFG_SYS_CSOR3           CFG_SYS_FPGA_CSOR
 248 #define CFG_SYS_CS3_FTIM0               CFG_SYS_FPGA_FTIM0
 249 #define CFG_SYS_CS3_FTIM1               CFG_SYS_FPGA_FTIM1
 250 #define CFG_SYS_CS3_FTIM2               CFG_SYS_FPGA_FTIM2
 251 #define CFG_SYS_CS3_FTIM3               CFG_SYS_FPGA_FTIM3
 252 #else
 253 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NOR0_CSPR_EXT
 254 #define CFG_SYS_CSPR0           CFG_SYS_NOR0_CSPR
 255 #define CFG_SYS_AMASK0          CFG_SYS_NOR_AMASK
 256 #define CFG_SYS_CSOR0           CFG_SYS_NOR_CSOR
 257 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NOR_FTIM0
 258 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NOR_FTIM1
 259 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NOR_FTIM2
 260 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NOR_FTIM3
 261 #define CFG_SYS_CSPR1_EXT               CFG_SYS_NOR1_CSPR_EXT
 262 #define CFG_SYS_CSPR1           CFG_SYS_NOR1_CSPR
 263 #define CFG_SYS_AMASK1          CFG_SYS_NOR_AMASK
 264 #define CFG_SYS_CSOR1           CFG_SYS_NOR_CSOR
 265 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NOR_FTIM0
 266 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NOR_FTIM1
 267 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NOR_FTIM2
 268 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NOR_FTIM3
 269 #define CFG_SYS_CSPR2_EXT               CFG_SYS_NAND_CSPR_EXT
 270 #define CFG_SYS_CSPR2           CFG_SYS_NAND_CSPR
 271 #define CFG_SYS_AMASK2          CFG_SYS_NAND_AMASK
 272 #define CFG_SYS_CSOR2           CFG_SYS_NAND_CSOR
 273 #define CFG_SYS_CS2_FTIM0               CFG_SYS_NAND_FTIM0
 274 #define CFG_SYS_CS2_FTIM1               CFG_SYS_NAND_FTIM1
 275 #define CFG_SYS_CS2_FTIM2               CFG_SYS_NAND_FTIM2
 276 #define CFG_SYS_CS2_FTIM3               CFG_SYS_NAND_FTIM3
 277 #define CFG_SYS_CSPR3_EXT               CFG_SYS_FPGA_CSPR_EXT
 278 #define CFG_SYS_CSPR3           CFG_SYS_FPGA_CSPR
 279 #define CFG_SYS_AMASK3          CFG_SYS_FPGA_AMASK
 280 #define CFG_SYS_CSOR3           CFG_SYS_FPGA_CSOR
 281 #define CFG_SYS_CS3_FTIM0               CFG_SYS_FPGA_FTIM0
 282 #define CFG_SYS_CS3_FTIM1               CFG_SYS_FPGA_FTIM1
 283 #define CFG_SYS_CS3_FTIM2               CFG_SYS_FPGA_FTIM2
 284 #define CFG_SYS_CS3_FTIM3               CFG_SYS_FPGA_FTIM3
 285 #endif
 286 #endif
 287
 288 /*
 289  * I2C bus multiplexer
 290  */
 291 #define I2C_MUX_PCA_ADDR_PRI            0x77
 292 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 293 #define I2C_RETIMER_ADDR                0x18
 294 #define I2C_MUX_CH_DEFAULT              0x8
 295 #define I2C_MUX_CH_CH7301               0xC
 296 #define I2C_MUX_CH5                     0xD
 297 #define I2C_MUX_CH6                     0xE
 298 #define I2C_MUX_CH7                     0xF
 299
 300 #define I2C_MUX_CH_VOL_MONITOR 0xa
 301
 302 /* Voltage monitor on channel 2*/
 303 #define I2C_VOL_MONITOR_ADDR           0x40
 304 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 305 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 306 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 307
 308 /* The lowest and highest voltage allowed for LS1046AQDS */
 309 #define VDD_MV_MIN                      819
 310 #define VDD_MV_MAX                      1212
 311
 312 /*
 313  * Miscellaneous configurable options
 314  */
 315
 316 /*
 317  * Environment
 318  */
 319
 320 #ifdef CONFIG_TFABOOT
 321 #define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; "   \
 322                            "env exists secureboot && esbc_halt;;"
 323 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd"      \
 324                            "env exists secureboot && esbc_halt;;"
 325 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "     \
 326                            "env exists secureboot && esbc_halt;;"
 327 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "   \
 328                            "env exists secureboot && esbc_halt;;"
 329 #endif
 330
 331 #include <asm/fsl_secure_boot.h>
 332
 333 #endif /* __LS1046AQDS_H__ */