include/configs/ls1046aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __LS1046AQDS_H__
   7 #define __LS1046AQDS_H__
   8
   9 #include "ls1046a_common.h"
  10
  11 #ifndef __ASSEMBLY__
  12 unsigned long get_board_sys_clk(void);
  13 #endif
  14
  15 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  16
  17 #define CONFIG_LAYERSCAPE_NS_ACCESS
  18
  19 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  20 /* Physical Memory Map */
  21 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  22
  23 #define SPD_EEPROM_ADDRESS              0x51
  24 #define CONFIG_SYS_SPD_BUS_NUM          0
  25
  26 #ifdef CONFIG_DDR_ECC
  27 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  28 #endif
  29
  30 /* DSPI */
  31 #ifdef CONFIG_FSL_DSPI
  32 #define CONFIG_SPI_FLASH_STMICRO        /* cs0 */
  33 #define CONFIG_SPI_FLASH_SST            /* cs1 */
  34 #define CONFIG_SPI_FLASH_EON            /* cs2 */
  35 #endif
  36
  37 #ifdef CONFIG_SYS_DPAA_FMAN
  38 #define RGMII_PHY1_ADDR         0x1
  39 #define RGMII_PHY2_ADDR         0x2
  40 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  41 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  42 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  43 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  44 /* PHY address on QSGMII riser card on slot 2 */
  45 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
  46 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
  47 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
  48 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
  49 #endif
  50
  51 /* IFC */
  52 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  53 #define CONFIG_FSL_IFC
  54 /*
  55  * CONFIG_SYS_FLASH_BASE has the final address (core view)
  56  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
  57  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  58  * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
  59  */
  60 #define CONFIG_SYS_FLASH_BASE                   0x60000000
  61 #define CONFIG_SYS_FLASH_BASE_PHYS              CONFIG_SYS_FLASH_BASE
  62 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY        0x00000000
  63
  64 #ifdef CONFIG_MTD_NOR_FLASH
  65 #define CONFIG_SYS_FLASH_QUIET_TEST
  66 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
  67 #endif
  68 #endif
  69
  70 /* LPUART */
  71 #ifdef CONFIG_LPUART
  72 #define CONFIG_LPUART_32B_REG
  73 #define CFG_UART_MUX_MASK       0x6
  74 #define CFG_UART_MUX_SHIFT      1
  75 #define CFG_LPUART_EN           0x2
  76 #endif
  77
  78 /* EEPROM */
  79 #define CONFIG_SYS_I2C_EEPROM_NXID
  80 #define CONFIG_SYS_EEPROM_BUS_NUM               0
  81
  82 /*
  83  * IFC Definitions
  84  */
  85 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  86 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  87 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  88                                 CSPR_PORT_SIZE_16 | \
  89                                 CSPR_MSEL_NOR | \
  90                                 CSPR_V)
  91 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
  92 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  93                                 + 0x8000000) | \
  94                                 CSPR_PORT_SIZE_16 | \
  95                                 CSPR_MSEL_NOR | \
  96                                 CSPR_V)
  97 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  98
  99 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 100                                         CSOR_NOR_TRHZ_80)
 101 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 102                                         FTIM0_NOR_TEADC(0x5) | \
 103                                         FTIM0_NOR_TAVDS(0x6) | \
 104                                         FTIM0_NOR_TEAHC(0x5))
 105 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 106                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
 107                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 108 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x8) | \
 109                                         FTIM2_NOR_TCH(0x8) | \
 110                                         FTIM2_NOR_TWPH(0xe) | \
 111                                         FTIM2_NOR_TWP(0x1c))
 112 #define CONFIG_SYS_NOR_FTIM3            0
 113
 114 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 115 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 116 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 117 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 118
 119 #define CONFIG_SYS_FLASH_EMPTY_INFO
 120 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 121                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 122
 123 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 124 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 125
 126 /*
 127  * NAND Flash Definitions
 128  */
 129 #define CONFIG_NAND_FSL_IFC
 130
 131 #define CONFIG_SYS_NAND_BASE            0x7e800000
 132 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 133
 134 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 135
 136 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 137                                 | CSPR_PORT_SIZE_8      \
 138                                 | CSPR_MSEL_NAND        \
 139                                 | CSPR_V)
 140 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 141 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 142                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 143                                 | CSOR_NAND_ECC_MODE_8  /* 8-bit ECC */ \
 144                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 145                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 146                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 147                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 148
 149 #define CONFIG_SYS_NAND_ONFI_DETECTION
 150
 151 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 152                                         FTIM0_NAND_TWP(0x18)   | \
 153                                         FTIM0_NAND_TWCHT(0x7) | \
 154                                         FTIM0_NAND_TWH(0xa))
 155 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 156                                         FTIM1_NAND_TWBE(0x39)  | \
 157                                         FTIM1_NAND_TRR(0xe)   | \
 158                                         FTIM1_NAND_TRP(0x18))
 159 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 160                                         FTIM2_NAND_TREH(0xa) | \
 161                                         FTIM2_NAND_TWHRE(0x1e))
 162 #define CONFIG_SYS_NAND_FTIM3           0x0
 163
 164 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 165 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 166 #define CONFIG_MTD_NAND_VERIFY_WRITE
 167 #endif
 168
 169 #ifdef CONFIG_NAND_BOOT
 170 #define CONFIG_SPL_PAD_TO               0x40000         /* block aligned */
 171 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
 172 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
 173 #endif
 174
 175 #if defined(CONFIG_TFABOOT) || \
 176         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 177 #define CONFIG_QIXIS_I2C_ACCESS
 178 #endif
 179
 180 /*
 181  * QIXIS Definitions
 182  */
 183 #define CONFIG_FSL_QIXIS
 184
 185 #ifdef CONFIG_FSL_QIXIS
 186 #define QIXIS_BASE                      0x7fb00000
 187 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 188 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 189 #define QIXIS_LBMAP_SWITCH              6
 190 #define QIXIS_LBMAP_MASK                0x0f
 191 #define QIXIS_LBMAP_SHIFT               0
 192 #define QIXIS_LBMAP_DFLTBANK            0x00
 193 #define QIXIS_LBMAP_ALTBANK             0x04
 194 #define QIXIS_LBMAP_NAND                0x09
 195 #define QIXIS_LBMAP_SD                  0x00
 196 #define QIXIS_LBMAP_SD_QSPI             0xff
 197 #define QIXIS_LBMAP_QSPI                0xff
 198 #define QIXIS_RCW_SRC_NAND              0x110
 199 #define QIXIS_RCW_SRC_SD                0x040
 200 #define QIXIS_RCW_SRC_QSPI              0x045
 201 #define QIXIS_RST_CTL_RESET             0x41
 202 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 203 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 204 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 205
 206 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 207 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 208                                         CSPR_PORT_SIZE_8 | \
 209                                         CSPR_MSEL_GPCM | \
 210                                         CSPR_V)
 211 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 212 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 213                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 214                                         CSOR_NOR_TRHZ_80)
 215
 216 /*
 217  * QIXIS Timing parameters for IFC GPCM
 218  */
 219 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xc) | \
 220                                         FTIM0_GPCM_TEADC(0x20) | \
 221                                         FTIM0_GPCM_TEAHC(0x10))
 222 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0x50) | \
 223                                         FTIM1_GPCM_TRAD(0x1f))
 224 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0x8) | \
 225                                         FTIM2_GPCM_TCH(0x8) | \
 226                                         FTIM2_GPCM_TWP(0xf0))
 227 #define CONFIG_SYS_FPGA_FTIM3           0x0
 228 #endif
 229
 230 #ifdef CONFIG_TFABOOT
 231 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 232 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 233 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 234 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 235 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 236 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 237 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 238 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 239 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 240 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 241 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 242 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 243 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 244 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 245 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 246 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 247 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 248 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 249 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 250 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 251 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 252 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 253 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 254 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 255 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 256 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 257 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 258 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 259 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 260 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 261 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 262 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 263 #else
 264 #ifdef CONFIG_NAND_BOOT
 265 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 266 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 267 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 268 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 269 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 270 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 271 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 272 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 273 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 274 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 275 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 276 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 277 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 278 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 279 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 280 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 281 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 282 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 283 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 284 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 285 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 286 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 287 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 288 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 289 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 290 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 291 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 292 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 293 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 294 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 295 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 296 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 297 #else
 298 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 299 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 300 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 301 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 302 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 303 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 304 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 305 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 306 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 307 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 308 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 309 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 310 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 311 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 312 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 313 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 314 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 315 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 316 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 317 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 318 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 319 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 320 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 321 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 322 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 323 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 324 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 325 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 326 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 327 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 328 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 329 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 330 #endif
 331 #endif
 332
 333 /*
 334  * I2C bus multiplexer
 335  */
 336 #define I2C_MUX_PCA_ADDR_PRI            0x77
 337 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 338 #define I2C_RETIMER_ADDR                0x18
 339 #define I2C_MUX_CH_DEFAULT              0x8
 340 #define I2C_MUX_CH_CH7301               0xC
 341 #define I2C_MUX_CH5                     0xD
 342 #define I2C_MUX_CH6                     0xE
 343 #define I2C_MUX_CH7                     0xF
 344
 345 #define I2C_MUX_CH_VOL_MONITOR 0xa
 346
 347 /* Voltage monitor on channel 2*/
 348 #define I2C_VOL_MONITOR_ADDR           0x40
 349 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 350 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 351 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 352
 353 #define CONFIG_VID_FLS_ENV              "ls1046aqds_vdd_mv"
 354 #ifndef CONFIG_SPL_BUILD
 355 #define CONFIG_VID
 356 #endif
 357 #define CONFIG_VOL_MONITOR_IR36021_SET
 358 #define CONFIG_VOL_MONITOR_INA220
 359 /* The lowest and highest voltage allowed for LS1046AQDS */
 360 #define VDD_MV_MIN                      819
 361 #define VDD_MV_MAX                      1212
 362
 363 /*
 364  * Miscellaneous configurable options
 365  */
 366
 367 #define CONFIG_SYS_HZ                   1000
 368
 369 #define CONFIG_SYS_INIT_SP_OFFSET \
 370         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 371
 372 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 373
 374 /*
 375  * Environment
 376  */
 377
 378 #undef CONFIG_BOOTCOMMAND
 379 #ifdef CONFIG_TFABOOT
 380 #define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; "   \
 381                            "env exists secureboot && esbc_halt;;"
 382 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd"      \
 383                            "env exists secureboot && esbc_halt;;"
 384 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "     \
 385                            "env exists secureboot && esbc_halt;;"
 386 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "   \
 387                            "env exists secureboot && esbc_halt;;"
 388 #else
 389 #if defined(CONFIG_QSPI_BOOT)
 390 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "      \
 391                            "env exists secureboot && esbc_halt;;"
 392 #elif defined(CONFIG_NAND_BOOT)
 393 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; "     \
 394                            "env exists secureboot && esbc_halt;;"
 395 #elif defined(CONFIG_SD_BOOT)
 396 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "       \
 397                            "env exists secureboot && esbc_halt;;"
 398 #else
 399 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "      \
 400                            "env exists secureboot && esbc_halt;;"
 401 #endif
 402 #endif
 403
 404 #include <asm/fsl_secure_boot.h>
 405
 406 #endif /* __LS1046AQDS_H__ */