include/configs/ls1046aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __LS1046AQDS_H__
   7 #define __LS1046AQDS_H__
   8
   9 #include "ls1046a_common.h"
  10
  11 #ifndef __ASSEMBLY__
  12 unsigned long get_board_sys_clk(void);
  13 unsigned long get_board_ddr_clk(void);
  14 #endif
  15
  16 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  17 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
  18
  19 #define CONFIG_SKIP_LOWLEVEL_INIT
  20
  21 #define CONFIG_LAYERSCAPE_NS_ACCESS
  22
  23 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  24 /* Physical Memory Map */
  25 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  26
  27 #define CONFIG_DDR_SPD
  28 #define SPD_EEPROM_ADDRESS              0x51
  29 #define CONFIG_SYS_SPD_BUS_NUM          0
  30
  31 #ifndef CONFIG_SPL
  32 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
  33 #endif
  34
  35 #define CONFIG_DDR_ECC
  36 #ifdef CONFIG_DDR_ECC
  37 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  38 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  39 #endif
  40
  41 /* DSPI */
  42 #ifdef CONFIG_FSL_DSPI
  43 #define CONFIG_SPI_FLASH_STMICRO        /* cs0 */
  44 #define CONFIG_SPI_FLASH_SST            /* cs1 */
  45 #define CONFIG_SPI_FLASH_EON            /* cs2 */
  46 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  47 #define CONFIG_SF_DEFAULT_BUS           1
  48 #define CONFIG_SF_DEFAULT_CS            0
  49 #endif
  50 #endif
  51
  52 /* QSPI */
  53 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  54 #ifdef CONFIG_FSL_QSPI
  55 #define CONFIG_SPI_FLASH_SPANSION
  56 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
  57 #define FSL_QSPI_FLASH_NUM              2
  58 #endif
  59 #endif
  60
  61 #ifdef CONFIG_SYS_DPAA_FMAN
  62 #define CONFIG_FMAN_ENET
  63 #define CONFIG_PHY_VITESSE
  64 #define CONFIG_PHY_REALTEK
  65 #define CONFIG_PHYLIB_10G
  66 #define RGMII_PHY1_ADDR         0x1
  67 #define RGMII_PHY2_ADDR         0x2
  68 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  69 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  70 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  71 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  72 /* PHY address on QSGMII riser card on slot 2 */
  73 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
  74 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
  75 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
  76 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
  77 #endif
  78
  79 #ifdef CONFIG_RAMBOOT_PBL
  80 #define CONFIG_SYS_FSL_PBL_PBI \
  81         board/freescale/ls1046aqds/ls1046aqds_pbi.cfg
  82 #endif
  83
  84 #ifdef CONFIG_NAND_BOOT
  85 #define CONFIG_SYS_FSL_PBL_RCW \
  86         board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg
  87 #endif
  88
  89 #ifdef CONFIG_SD_BOOT
  90 #ifdef CONFIG_SD_BOOT_QSPI
  91 #define CONFIG_SYS_FSL_PBL_RCW \
  92         board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg
  93 #else
  94 #define CONFIG_SYS_FSL_PBL_RCW \
  95         board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg
  96 #endif
  97 #endif
  98
  99 /* IFC */
 100 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 101 #define CONFIG_FSL_IFC
 102 /*
 103  * CONFIG_SYS_FLASH_BASE has the final address (core view)
 104  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
 105  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
 106  * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
 107  */
 108 #define CONFIG_SYS_FLASH_BASE                   0x60000000
 109 #define CONFIG_SYS_FLASH_BASE_PHYS              CONFIG_SYS_FLASH_BASE
 110 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY        0x00000000
 111
 112 #ifdef CONFIG_MTD_NOR_FLASH
 113 #define CONFIG_SYS_FLASH_QUIET_TEST
 114 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 115 #endif
 116 #endif
 117
 118 /* LPUART */
 119 #ifdef CONFIG_LPUART
 120 #define CONFIG_LPUART_32B_REG
 121 #define CFG_UART_MUX_MASK       0x6
 122 #define CFG_UART_MUX_SHIFT      1
 123 #define CFG_LPUART_EN           0x2
 124 #endif
 125
 126 /* EEPROM */
 127 #define CONFIG_ID_EEPROM
 128 #define CONFIG_SYS_I2C_EEPROM_NXID
 129 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 130 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x57
 131 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 132 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 133 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 134
 135 /*
 136  * IFC Definitions
 137  */
 138 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 139 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
 140 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 141                                 CSPR_PORT_SIZE_16 | \
 142                                 CSPR_MSEL_NOR | \
 143                                 CSPR_V)
 144 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
 145 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 146                                 + 0x8000000) | \
 147                                 CSPR_PORT_SIZE_16 | \
 148                                 CSPR_MSEL_NOR | \
 149                                 CSPR_V)
 150 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 151
 152 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 153                                         CSOR_NOR_TRHZ_80)
 154 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 155                                         FTIM0_NOR_TEADC(0x5) | \
 156                                         FTIM0_NOR_TAVDS(0x6) | \
 157                                         FTIM0_NOR_TEAHC(0x5))
 158 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 159                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
 160                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 161 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x8) | \
 162                                         FTIM2_NOR_TCH(0x8) | \
 163                                         FTIM2_NOR_TWPH(0xe) | \
 164                                         FTIM2_NOR_TWP(0x1c))
 165 #define CONFIG_SYS_NOR_FTIM3            0
 166
 167 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 168 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 169 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 170 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 171
 172 #define CONFIG_SYS_FLASH_EMPTY_INFO
 173 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 174                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 175
 176 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 177 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 178
 179 /*
 180  * NAND Flash Definitions
 181  */
 182 #define CONFIG_NAND_FSL_IFC
 183
 184 #define CONFIG_SYS_NAND_BASE            0x7e800000
 185 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 186
 187 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 188
 189 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 190                                 | CSPR_PORT_SIZE_8      \
 191                                 | CSPR_MSEL_NAND        \
 192                                 | CSPR_V)
 193 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 194 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 195                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 196                                 | CSOR_NAND_ECC_MODE_8  /* 8-bit ECC */ \
 197                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 198                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 199                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 200                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 201
 202 #define CONFIG_SYS_NAND_ONFI_DETECTION
 203
 204 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 205                                         FTIM0_NAND_TWP(0x18)   | \
 206                                         FTIM0_NAND_TWCHT(0x7) | \
 207                                         FTIM0_NAND_TWH(0xa))
 208 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 209                                         FTIM1_NAND_TWBE(0x39)  | \
 210                                         FTIM1_NAND_TRR(0xe)   | \
 211                                         FTIM1_NAND_TRP(0x18))
 212 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 213                                         FTIM2_NAND_TREH(0xa) | \
 214                                         FTIM2_NAND_TWHRE(0x1e))
 215 #define CONFIG_SYS_NAND_FTIM3           0x0
 216
 217 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 218 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 219 #define CONFIG_MTD_NAND_VERIFY_WRITE
 220
 221 #define CONFIG_SYS_NAND_BLOCK_SIZE      (256 * 1024)
 222 #endif
 223
 224 #ifdef CONFIG_NAND_BOOT
 225 #define CONFIG_SPL_PAD_TO               0x40000         /* block aligned */
 226 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
 227 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
 228 #endif
 229
 230 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 231 #define CONFIG_QIXIS_I2C_ACCESS
 232 #define CONFIG_SYS_I2C_EARLY_INIT
 233 #endif
 234
 235 /*
 236  * QIXIS Definitions
 237  */
 238 #define CONFIG_FSL_QIXIS
 239
 240 #ifdef CONFIG_FSL_QIXIS
 241 #define QIXIS_BASE                      0x7fb00000
 242 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 243 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 244 #define QIXIS_LBMAP_SWITCH              6
 245 #define QIXIS_LBMAP_MASK                0x0f
 246 #define QIXIS_LBMAP_SHIFT               0
 247 #define QIXIS_LBMAP_DFLTBANK            0x00
 248 #define QIXIS_LBMAP_ALTBANK             0x04
 249 #define QIXIS_LBMAP_NAND                0x09
 250 #define QIXIS_LBMAP_SD                  0x00
 251 #define QIXIS_LBMAP_SD_QSPI             0xff
 252 #define QIXIS_LBMAP_QSPI                0xff
 253 #define QIXIS_RCW_SRC_NAND              0x110
 254 #define QIXIS_RCW_SRC_SD                0x040
 255 #define QIXIS_RCW_SRC_QSPI              0x045
 256 #define QIXIS_RST_CTL_RESET             0x41
 257 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 258 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 259 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 260
 261 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 262 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 263                                         CSPR_PORT_SIZE_8 | \
 264                                         CSPR_MSEL_GPCM | \
 265                                         CSPR_V)
 266 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 267 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 268                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 269                                         CSOR_NOR_TRHZ_80)
 270
 271 /*
 272  * QIXIS Timing parameters for IFC GPCM
 273  */
 274 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xc) | \
 275                                         FTIM0_GPCM_TEADC(0x20) | \
 276                                         FTIM0_GPCM_TEAHC(0x10))
 277 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0x50) | \
 278                                         FTIM1_GPCM_TRAD(0x1f))
 279 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0x8) | \
 280                                         FTIM2_GPCM_TCH(0x8) | \
 281                                         FTIM2_GPCM_TWP(0xf0))
 282 #define CONFIG_SYS_FPGA_FTIM3           0x0
 283 #endif
 284
 285 #ifdef CONFIG_NAND_BOOT
 286 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 287 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 288 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 289 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 290 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 291 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 292 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 293 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 294 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 295 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 296 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 297 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 298 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 299 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 300 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 301 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 302 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 303 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 304 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 305 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 306 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 307 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 308 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 309 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 310 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 311 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 312 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 313 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 314 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 315 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 316 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 317 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 318 #else
 319 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 320 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 321 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 322 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 323 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 324 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 325 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 326 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 327 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 328 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 329 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 330 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 331 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 332 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 333 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 334 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 335 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 336 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 337 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 338 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 339 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 340 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 341 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 342 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 343 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 344 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 345 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 346 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 347 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 348 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 349 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 350 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 351 #endif
 352
 353 /*
 354  * I2C bus multiplexer
 355  */
 356 #define I2C_MUX_PCA_ADDR_PRI            0x77
 357 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 358 #define I2C_RETIMER_ADDR                0x18
 359 #define I2C_MUX_CH_DEFAULT              0x8
 360 #define I2C_MUX_CH_CH7301               0xC
 361 #define I2C_MUX_CH5                     0xD
 362 #define I2C_MUX_CH6                     0xE
 363 #define I2C_MUX_CH7                     0xF
 364
 365 #define I2C_MUX_CH_VOL_MONITOR 0xa
 366
 367 /* Voltage monitor on channel 2*/
 368 #define I2C_VOL_MONITOR_ADDR           0x40
 369 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 370 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 371 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 372
 373 #define CONFIG_VID_FLS_ENV              "ls1046aqds_vdd_mv"
 374 #ifndef CONFIG_SPL_BUILD
 375 #define CONFIG_VID
 376 #endif
 377 #define CONFIG_VOL_MONITOR_IR36021_SET
 378 #define CONFIG_VOL_MONITOR_INA220
 379 /* The lowest and highest voltage allowed for LS1046AQDS */
 380 #define VDD_MV_MIN                      819
 381 #define VDD_MV_MAX                      1212
 382
 383 /*
 384  * Miscellaneous configurable options
 385  */
 386
 387 #define CONFIG_SYS_MEMTEST_START        0x80000000
 388 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
 389
 390 #define CONFIG_SYS_HZ                   1000
 391
 392 #define CONFIG_SYS_INIT_SP_OFFSET \
 393         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 394
 395 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 396
 397 /*
 398  * Environment
 399  */
 400 #define CONFIG_ENV_OVERWRITE
 401
 402 #ifdef CONFIG_NAND_BOOT
 403 #define CONFIG_ENV_SIZE                 0x2000
 404 #define CONFIG_ENV_OFFSET               (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 405 #elif defined(CONFIG_SD_BOOT)
 406 #define CONFIG_ENV_OFFSET               (3 * 1024 * 1024)
 407 #define CONFIG_SYS_MMC_ENV_DEV          0
 408 #define CONFIG_ENV_SIZE                 0x2000
 409 #elif defined(CONFIG_QSPI_BOOT)
 410 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 411 #define CONFIG_ENV_OFFSET               0x300000        /* 3MB */
 412 #define CONFIG_ENV_SECT_SIZE            0x10000
 413 #else
 414 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x300000)
 415 #define CONFIG_ENV_SECT_SIZE            0x20000
 416 #define CONFIG_ENV_SIZE                 0x20000
 417 #endif
 418
 419 #define CONFIG_CMDLINE_TAG
 420
 421 #undef CONFIG_BOOTCOMMAND
 422 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 423 #define CONFIG_BOOTCOMMAND              "sf probe && sf read $kernel_load "    \
 424                                         "e0000 f00000 && bootm $kernel_load"
 425 #else
 426 #define CONFIG_BOOTCOMMAND              "cp.b $kernel_start $kernel_load "     \
 427                                         "$kernel_size && bootm $kernel_load"
 428 #endif
 429
 430 #include <asm/fsl_secure_boot.h>
 431
 432 #endif /* __LS1046AQDS_H__ */