1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016 Freescale Semiconductor, Inc.
6 #ifndef __LS1046AQDS_H__
7 #define __LS1046AQDS_H__
9 #include "ls1046a_common.h"
12 unsigned long get_board_sys_clk(void);
13 unsigned long get_board_ddr_clk(void);
16 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
17 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
19 #define CONFIG_SKIP_LOWLEVEL_INIT
21 #define CONFIG_LAYERSCAPE_NS_ACCESS
23 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
24 /* Physical Memory Map */
25 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
27 #define CONFIG_DDR_SPD
28 #define SPD_EEPROM_ADDRESS 0x51
29 #define CONFIG_SYS_SPD_BUS_NUM 0
31 #define CONFIG_DDR_ECC
33 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
34 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
38 #ifdef CONFIG_FSL_DSPI
39 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */
40 #define CONFIG_SPI_FLASH_SST /* cs1 */
41 #define CONFIG_SPI_FLASH_EON /* cs2 */
44 #ifdef CONFIG_SYS_DPAA_FMAN
45 #define RGMII_PHY1_ADDR 0x1
46 #define RGMII_PHY2_ADDR 0x2
47 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
48 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
49 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
50 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
51 /* PHY address on QSGMII riser card on slot 2 */
52 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
53 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
54 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
55 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
58 #ifdef CONFIG_RAMBOOT_PBL
59 #define CONFIG_SYS_FSL_PBL_PBI \
60 board/freescale/ls1046aqds/ls1046aqds_pbi.cfg
63 #ifdef CONFIG_NAND_BOOT
64 #define CONFIG_SYS_FSL_PBL_RCW \
65 board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg
69 #ifdef CONFIG_SD_BOOT_QSPI
70 #define CONFIG_SYS_FSL_PBL_RCW \
71 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg
73 #define CONFIG_SYS_FSL_PBL_RCW \
74 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg
79 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
80 #define CONFIG_FSL_IFC
82 * CONFIG_SYS_FLASH_BASE has the final address (core view)
83 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
84 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
85 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
87 #define CONFIG_SYS_FLASH_BASE 0x60000000
88 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
89 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
91 #ifdef CONFIG_MTD_NOR_FLASH
92 #define CONFIG_SYS_FLASH_QUIET_TEST
93 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
99 #define CONFIG_LPUART_32B_REG
100 #define CFG_UART_MUX_MASK 0x6
101 #define CFG_UART_MUX_SHIFT 1
102 #define CFG_LPUART_EN 0x2
106 #define CONFIG_SYS_I2C_EEPROM_NXID
107 #define CONFIG_SYS_EEPROM_BUS_NUM 0
112 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
113 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
114 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
115 CSPR_PORT_SIZE_16 | \
118 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
119 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
121 CSPR_PORT_SIZE_16 | \
124 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
126 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
128 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
129 FTIM0_NOR_TEADC(0x5) | \
130 FTIM0_NOR_TAVDS(0x6) | \
131 FTIM0_NOR_TEAHC(0x5))
132 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
133 FTIM1_NOR_TRAD_NOR(0x1a) | \
134 FTIM1_NOR_TSEQRAD_NOR(0x13))
135 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \
136 FTIM2_NOR_TCH(0x8) | \
137 FTIM2_NOR_TWPH(0xe) | \
139 #define CONFIG_SYS_NOR_FTIM3 0
141 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
142 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
143 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
144 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
146 #define CONFIG_SYS_FLASH_EMPTY_INFO
147 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
148 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
150 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
151 #define CONFIG_SYS_WRITE_SWAPPED_DATA
154 * NAND Flash Definitions
156 #define CONFIG_NAND_FSL_IFC
158 #define CONFIG_SYS_NAND_BASE 0x7e800000
159 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
161 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
163 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
167 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
168 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
169 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
170 | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
171 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
172 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
173 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
174 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
176 #define CONFIG_SYS_NAND_ONFI_DETECTION
178 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
179 FTIM0_NAND_TWP(0x18) | \
180 FTIM0_NAND_TWCHT(0x7) | \
182 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
183 FTIM1_NAND_TWBE(0x39) | \
184 FTIM1_NAND_TRR(0xe) | \
185 FTIM1_NAND_TRP(0x18))
186 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
187 FTIM2_NAND_TREH(0xa) | \
188 FTIM2_NAND_TWHRE(0x1e))
189 #define CONFIG_SYS_NAND_FTIM3 0x0
191 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
192 #define CONFIG_SYS_MAX_NAND_DEVICE 1
193 #define CONFIG_MTD_NAND_VERIFY_WRITE
195 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
198 #ifdef CONFIG_NAND_BOOT
199 #define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */
200 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
201 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
204 #if defined(CONFIG_TFABOOT) || \
205 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
206 #define CONFIG_QIXIS_I2C_ACCESS
207 #define CONFIG_SYS_I2C_EARLY_INIT
213 #define CONFIG_FSL_QIXIS
215 #ifdef CONFIG_FSL_QIXIS
216 #define QIXIS_BASE 0x7fb00000
217 #define QIXIS_BASE_PHYS QIXIS_BASE
218 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
219 #define QIXIS_LBMAP_SWITCH 6
220 #define QIXIS_LBMAP_MASK 0x0f
221 #define QIXIS_LBMAP_SHIFT 0
222 #define QIXIS_LBMAP_DFLTBANK 0x00
223 #define QIXIS_LBMAP_ALTBANK 0x04
224 #define QIXIS_LBMAP_NAND 0x09
225 #define QIXIS_LBMAP_SD 0x00
226 #define QIXIS_LBMAP_SD_QSPI 0xff
227 #define QIXIS_LBMAP_QSPI 0xff
228 #define QIXIS_RCW_SRC_NAND 0x110
229 #define QIXIS_RCW_SRC_SD 0x040
230 #define QIXIS_RCW_SRC_QSPI 0x045
231 #define QIXIS_RST_CTL_RESET 0x41
232 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
233 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
234 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
236 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
237 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
241 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
242 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
243 CSOR_NOR_NOR_MODE_AVD_NOR | \
247 * QIXIS Timing parameters for IFC GPCM
249 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
250 FTIM0_GPCM_TEADC(0x20) | \
251 FTIM0_GPCM_TEAHC(0x10))
252 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
253 FTIM1_GPCM_TRAD(0x1f))
254 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
255 FTIM2_GPCM_TCH(0x8) | \
256 FTIM2_GPCM_TWP(0xf0))
257 #define CONFIG_SYS_FPGA_FTIM3 0x0
260 #ifdef CONFIG_TFABOOT
261 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
262 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
263 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
264 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
265 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
266 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
267 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
268 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
269 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
270 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
271 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
272 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
273 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
274 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
275 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
276 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
277 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
278 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
279 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
280 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
281 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
282 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
283 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
284 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
285 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
286 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
287 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
288 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
289 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
290 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
291 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
292 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
294 #ifdef CONFIG_NAND_BOOT
295 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
296 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
297 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
298 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
299 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
300 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
301 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
302 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
303 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
304 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
305 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
306 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
307 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
308 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
309 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
310 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
311 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
312 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
313 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
314 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
315 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
316 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
317 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
318 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
319 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
320 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
321 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
322 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
323 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
324 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
325 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
326 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
328 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
329 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
330 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
331 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
332 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
333 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
334 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
335 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
336 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
337 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
338 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
339 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
340 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
341 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
342 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
343 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
344 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
345 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
346 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
347 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
348 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
349 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
350 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
351 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
352 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
353 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
354 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
355 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
356 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
357 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
358 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
359 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
364 * I2C bus multiplexer
366 #define I2C_MUX_PCA_ADDR_PRI 0x77
367 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
368 #define I2C_RETIMER_ADDR 0x18
369 #define I2C_MUX_CH_DEFAULT 0x8
370 #define I2C_MUX_CH_CH7301 0xC
371 #define I2C_MUX_CH5 0xD
372 #define I2C_MUX_CH6 0xE
373 #define I2C_MUX_CH7 0xF
375 #define I2C_MUX_CH_VOL_MONITOR 0xa
377 /* Voltage monitor on channel 2*/
378 #define I2C_VOL_MONITOR_ADDR 0x40
379 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
380 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
381 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
383 #define CONFIG_VID_FLS_ENV "ls1046aqds_vdd_mv"
384 #ifndef CONFIG_SPL_BUILD
387 #define CONFIG_VOL_MONITOR_IR36021_SET
388 #define CONFIG_VOL_MONITOR_INA220
389 /* The lowest and highest voltage allowed for LS1046AQDS */
390 #define VDD_MV_MIN 819
391 #define VDD_MV_MAX 1212
394 * Miscellaneous configurable options
397 #define CONFIG_SYS_HZ 1000
399 #define CONFIG_SYS_INIT_SP_OFFSET \
400 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
402 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
408 #define CONFIG_CMDLINE_TAG
410 #undef CONFIG_BOOTCOMMAND
411 #ifdef CONFIG_TFABOOT
412 #define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \
413 "env exists secureboot && esbc_halt;;"
414 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd" \
415 "env exists secureboot && esbc_halt;;"
416 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
417 "env exists secureboot && esbc_halt;;"
418 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
419 "env exists secureboot && esbc_halt;;"
421 #if defined(CONFIG_QSPI_BOOT)
422 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
423 "env exists secureboot && esbc_halt;;"
424 #elif defined(CONFIG_NAND_BOOT)
425 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \
426 "env exists secureboot && esbc_halt;;"
427 #elif defined(CONFIG_SD_BOOT)
428 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
429 "env exists secureboot && esbc_halt;;"
431 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
432 "env exists secureboot && esbc_halt;;"
436 #include <asm/fsl_secure_boot.h>
438 #endif /* __LS1046AQDS_H__ */