1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016 Freescale Semiconductor, Inc.
6 #ifndef __LS1046AQDS_H__
7 #define __LS1046AQDS_H__
9 #include "ls1046a_common.h"
11 /* Physical Memory Map */
13 #define SPD_EEPROM_ADDRESS 0x51
16 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
19 #ifdef CONFIG_SYS_DPAA_FMAN
20 #define RGMII_PHY1_ADDR 0x1
21 #define RGMII_PHY2_ADDR 0x2
22 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
23 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
24 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
25 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
26 /* PHY address on QSGMII riser card on slot 2 */
27 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
28 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
29 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
30 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
34 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
36 * CONFIG_SYS_FLASH_BASE has the final address (core view)
37 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
38 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
39 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
41 #define CONFIG_SYS_FLASH_BASE 0x60000000
42 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
43 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
45 #ifdef CONFIG_MTD_NOR_FLASH
46 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
52 #define CFG_UART_MUX_MASK 0x6
53 #define CFG_UART_MUX_SHIFT 1
54 #define CFG_LPUART_EN 0x2
58 #define CONFIG_SYS_I2C_EEPROM_NXID
59 #define CONFIG_SYS_EEPROM_BUS_NUM 0
64 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
65 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
66 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
70 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
71 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
76 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
78 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
80 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
81 FTIM0_NOR_TEADC(0x5) | \
82 FTIM0_NOR_TAVDS(0x6) | \
84 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
85 FTIM1_NOR_TRAD_NOR(0x1a) | \
86 FTIM1_NOR_TSEQRAD_NOR(0x13))
87 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \
88 FTIM2_NOR_TCH(0x8) | \
89 FTIM2_NOR_TWPH(0xe) | \
91 #define CONFIG_SYS_NOR_FTIM3 0
93 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
94 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
96 #define CONFIG_SYS_WRITE_SWAPPED_DATA
99 * NAND Flash Definitions
102 #define CONFIG_SYS_NAND_BASE 0x7e800000
103 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
105 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
107 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
111 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
112 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
113 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
114 | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
115 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
116 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
117 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
118 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
120 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
121 FTIM0_NAND_TWP(0x18) | \
122 FTIM0_NAND_TWCHT(0x7) | \
124 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
125 FTIM1_NAND_TWBE(0x39) | \
126 FTIM1_NAND_TRR(0xe) | \
127 FTIM1_NAND_TRP(0x18))
128 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
129 FTIM2_NAND_TREH(0xa) | \
130 FTIM2_NAND_TWHRE(0x1e))
131 #define CONFIG_SYS_NAND_FTIM3 0x0
133 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
134 #define CONFIG_SYS_MAX_NAND_DEVICE 1
135 #define CONFIG_MTD_NAND_VERIFY_WRITE
138 #ifdef CONFIG_NAND_BOOT
139 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
142 #if defined(CONFIG_TFABOOT) || \
143 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
150 #ifdef CONFIG_FSL_QIXIS
151 #define QIXIS_BASE 0x7fb00000
152 #define QIXIS_BASE_PHYS QIXIS_BASE
153 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
154 #define QIXIS_LBMAP_SWITCH 6
155 #define QIXIS_LBMAP_MASK 0x0f
156 #define QIXIS_LBMAP_SHIFT 0
157 #define QIXIS_LBMAP_DFLTBANK 0x00
158 #define QIXIS_LBMAP_ALTBANK 0x04
159 #define QIXIS_LBMAP_NAND 0x09
160 #define QIXIS_LBMAP_SD 0x00
161 #define QIXIS_LBMAP_SD_QSPI 0xff
162 #define QIXIS_LBMAP_QSPI 0xff
163 #define QIXIS_RCW_SRC_NAND 0x110
164 #define QIXIS_RCW_SRC_SD 0x040
165 #define QIXIS_RCW_SRC_QSPI 0x045
166 #define QIXIS_RST_CTL_RESET 0x41
167 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
168 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
169 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
171 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
172 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
176 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
177 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
178 CSOR_NOR_NOR_MODE_AVD_NOR | \
182 * QIXIS Timing parameters for IFC GPCM
184 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
185 FTIM0_GPCM_TEADC(0x20) | \
186 FTIM0_GPCM_TEAHC(0x10))
187 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
188 FTIM1_GPCM_TRAD(0x1f))
189 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
190 FTIM2_GPCM_TCH(0x8) | \
191 FTIM2_GPCM_TWP(0xf0))
192 #define CONFIG_SYS_FPGA_FTIM3 0x0
195 #ifdef CONFIG_TFABOOT
196 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
197 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
198 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
199 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
200 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
201 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
202 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
203 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
204 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
205 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
206 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
207 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
208 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
209 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
210 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
211 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
212 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
213 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
214 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
215 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
216 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
217 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
218 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
219 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
220 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
221 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
222 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
223 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
224 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
225 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
226 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
227 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
229 #ifdef CONFIG_NAND_BOOT
230 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
231 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
232 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
233 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
234 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
235 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
236 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
237 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
238 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
239 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
240 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
241 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
242 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
243 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
244 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
245 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
246 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
247 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
248 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
249 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
250 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
251 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
252 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
253 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
254 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
255 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
256 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
257 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
258 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
259 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
260 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
261 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
263 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
264 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
265 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
266 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
267 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
268 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
269 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
270 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
271 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
272 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
273 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
274 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
275 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
276 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
277 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
278 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
279 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
280 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
281 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
282 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
283 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
284 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
285 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
286 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
287 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
288 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
289 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
290 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
291 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
292 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
293 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
294 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
299 * I2C bus multiplexer
301 #define I2C_MUX_PCA_ADDR_PRI 0x77
302 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
303 #define I2C_RETIMER_ADDR 0x18
304 #define I2C_MUX_CH_DEFAULT 0x8
305 #define I2C_MUX_CH_CH7301 0xC
306 #define I2C_MUX_CH5 0xD
307 #define I2C_MUX_CH6 0xE
308 #define I2C_MUX_CH7 0xF
310 #define I2C_MUX_CH_VOL_MONITOR 0xa
312 /* Voltage monitor on channel 2*/
313 #define I2C_VOL_MONITOR_ADDR 0x40
314 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
315 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
316 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
318 /* The lowest and highest voltage allowed for LS1046AQDS */
319 #define VDD_MV_MIN 819
320 #define VDD_MV_MAX 1212
323 * Miscellaneous configurable options
330 #ifdef CONFIG_TFABOOT
331 #define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \
332 "env exists secureboot && esbc_halt;;"
333 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd" \
334 "env exists secureboot && esbc_halt;;"
335 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
336 "env exists secureboot && esbc_halt;;"
337 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
338 "env exists secureboot && esbc_halt;;"
341 #include <asm/fsl_secure_boot.h>
343 #endif /* __LS1046AQDS_H__ */