1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016 Freescale Semiconductor, Inc.
6 #ifndef __LS1046AQDS_H__
7 #define __LS1046AQDS_H__
9 #include "ls1046a_common.h"
12 unsigned long get_board_sys_clk(void);
13 unsigned long get_board_ddr_clk(void);
16 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
17 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
19 #define CONFIG_SKIP_LOWLEVEL_INIT
21 #define CONFIG_LAYERSCAPE_NS_ACCESS
23 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
24 /* Physical Memory Map */
25 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
27 #define CONFIG_DDR_SPD
28 #define SPD_EEPROM_ADDRESS 0x51
29 #define CONFIG_SYS_SPD_BUS_NUM 0
31 #define CONFIG_DDR_ECC
33 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
34 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
38 #ifdef CONFIG_FSL_DSPI
39 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */
40 #define CONFIG_SPI_FLASH_SST /* cs1 */
41 #define CONFIG_SPI_FLASH_EON /* cs2 */
42 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
43 #define CONFIG_SF_DEFAULT_BUS 1
44 #define CONFIG_SF_DEFAULT_CS 0
49 #if defined(CONFIG_TFABOOT) || \
50 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
51 #ifdef CONFIG_FSL_QSPI
52 #define CONFIG_SPI_FLASH_SPANSION
53 #define FSL_QSPI_FLASH_SIZE (1 << 24)
54 #define FSL_QSPI_FLASH_NUM 2
58 #ifdef CONFIG_SYS_DPAA_FMAN
59 #define CONFIG_FMAN_ENET
60 #define CONFIG_PHY_VITESSE
61 #define CONFIG_PHY_REALTEK
62 #define CONFIG_PHYLIB_10G
63 #define RGMII_PHY1_ADDR 0x1
64 #define RGMII_PHY2_ADDR 0x2
65 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
66 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
67 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
68 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
69 /* PHY address on QSGMII riser card on slot 2 */
70 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
71 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
72 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
73 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
76 #ifdef CONFIG_RAMBOOT_PBL
77 #define CONFIG_SYS_FSL_PBL_PBI \
78 board/freescale/ls1046aqds/ls1046aqds_pbi.cfg
81 #ifdef CONFIG_NAND_BOOT
82 #define CONFIG_SYS_FSL_PBL_RCW \
83 board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg
87 #ifdef CONFIG_SD_BOOT_QSPI
88 #define CONFIG_SYS_FSL_PBL_RCW \
89 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg
91 #define CONFIG_SYS_FSL_PBL_RCW \
92 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg
97 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
98 #define CONFIG_FSL_IFC
100 * CONFIG_SYS_FLASH_BASE has the final address (core view)
101 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
102 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
103 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
105 #define CONFIG_SYS_FLASH_BASE 0x60000000
106 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
107 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
109 #ifdef CONFIG_MTD_NOR_FLASH
110 #define CONFIG_SYS_FLASH_QUIET_TEST
111 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
117 #define CONFIG_LPUART_32B_REG
118 #define CFG_UART_MUX_MASK 0x6
119 #define CFG_UART_MUX_SHIFT 1
120 #define CFG_LPUART_EN 0x2
124 #define CONFIG_ID_EEPROM
125 #define CONFIG_SYS_I2C_EEPROM_NXID
126 #define CONFIG_SYS_EEPROM_BUS_NUM 0
127 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
128 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
129 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
130 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
135 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
136 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
137 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
138 CSPR_PORT_SIZE_16 | \
141 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
142 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
144 CSPR_PORT_SIZE_16 | \
147 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
149 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
151 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
152 FTIM0_NOR_TEADC(0x5) | \
153 FTIM0_NOR_TAVDS(0x6) | \
154 FTIM0_NOR_TEAHC(0x5))
155 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
156 FTIM1_NOR_TRAD_NOR(0x1a) | \
157 FTIM1_NOR_TSEQRAD_NOR(0x13))
158 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \
159 FTIM2_NOR_TCH(0x8) | \
160 FTIM2_NOR_TWPH(0xe) | \
162 #define CONFIG_SYS_NOR_FTIM3 0
164 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
165 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
166 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
167 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
169 #define CONFIG_SYS_FLASH_EMPTY_INFO
170 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
171 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
173 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
174 #define CONFIG_SYS_WRITE_SWAPPED_DATA
177 * NAND Flash Definitions
179 #define CONFIG_NAND_FSL_IFC
181 #define CONFIG_SYS_NAND_BASE 0x7e800000
182 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
184 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
186 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
190 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
191 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
192 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
193 | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
194 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
195 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
196 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
197 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
199 #define CONFIG_SYS_NAND_ONFI_DETECTION
201 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
202 FTIM0_NAND_TWP(0x18) | \
203 FTIM0_NAND_TWCHT(0x7) | \
205 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
206 FTIM1_NAND_TWBE(0x39) | \
207 FTIM1_NAND_TRR(0xe) | \
208 FTIM1_NAND_TRP(0x18))
209 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
210 FTIM2_NAND_TREH(0xa) | \
211 FTIM2_NAND_TWHRE(0x1e))
212 #define CONFIG_SYS_NAND_FTIM3 0x0
214 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
215 #define CONFIG_SYS_MAX_NAND_DEVICE 1
216 #define CONFIG_MTD_NAND_VERIFY_WRITE
218 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
221 #ifdef CONFIG_NAND_BOOT
222 #define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */
223 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
224 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
227 #if defined(CONFIG_TFABOOT) || \
228 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
229 #define CONFIG_QIXIS_I2C_ACCESS
230 #define CONFIG_SYS_I2C_EARLY_INIT
236 #define CONFIG_FSL_QIXIS
238 #ifdef CONFIG_FSL_QIXIS
239 #define QIXIS_BASE 0x7fb00000
240 #define QIXIS_BASE_PHYS QIXIS_BASE
241 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
242 #define QIXIS_LBMAP_SWITCH 6
243 #define QIXIS_LBMAP_MASK 0x0f
244 #define QIXIS_LBMAP_SHIFT 0
245 #define QIXIS_LBMAP_DFLTBANK 0x00
246 #define QIXIS_LBMAP_ALTBANK 0x04
247 #define QIXIS_LBMAP_NAND 0x09
248 #define QIXIS_LBMAP_SD 0x00
249 #define QIXIS_LBMAP_SD_QSPI 0xff
250 #define QIXIS_LBMAP_QSPI 0xff
251 #define QIXIS_RCW_SRC_NAND 0x110
252 #define QIXIS_RCW_SRC_SD 0x040
253 #define QIXIS_RCW_SRC_QSPI 0x045
254 #define QIXIS_RST_CTL_RESET 0x41
255 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
256 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
257 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
259 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
260 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
264 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
265 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
266 CSOR_NOR_NOR_MODE_AVD_NOR | \
270 * QIXIS Timing parameters for IFC GPCM
272 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
273 FTIM0_GPCM_TEADC(0x20) | \
274 FTIM0_GPCM_TEAHC(0x10))
275 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
276 FTIM1_GPCM_TRAD(0x1f))
277 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
278 FTIM2_GPCM_TCH(0x8) | \
279 FTIM2_GPCM_TWP(0xf0))
280 #define CONFIG_SYS_FPGA_FTIM3 0x0
283 #ifdef CONFIG_TFABOOT
284 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
285 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
286 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
287 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
288 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
289 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
290 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
291 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
292 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
293 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
294 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
295 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
296 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
297 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
298 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
299 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
300 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
301 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
302 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
303 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
304 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
305 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
306 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
307 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
308 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
309 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
310 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
311 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
312 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
313 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
314 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
315 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
317 #ifdef CONFIG_NAND_BOOT
318 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
319 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
320 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
321 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
322 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
323 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
324 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
325 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
326 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
327 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
328 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
329 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
330 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
331 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
332 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
333 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
334 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
335 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
336 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
337 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
338 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
339 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
340 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
341 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
342 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
343 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
344 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
345 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
346 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
347 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
348 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
349 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
351 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
352 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
353 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
354 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
355 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
356 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
357 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
358 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
359 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
360 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
361 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
362 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
363 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
364 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
365 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
366 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
367 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
368 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
369 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
370 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
371 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
372 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
373 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
374 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
375 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
376 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
377 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
378 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
379 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
380 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
381 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
382 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
387 * I2C bus multiplexer
389 #define I2C_MUX_PCA_ADDR_PRI 0x77
390 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
391 #define I2C_RETIMER_ADDR 0x18
392 #define I2C_MUX_CH_DEFAULT 0x8
393 #define I2C_MUX_CH_CH7301 0xC
394 #define I2C_MUX_CH5 0xD
395 #define I2C_MUX_CH6 0xE
396 #define I2C_MUX_CH7 0xF
398 #define I2C_MUX_CH_VOL_MONITOR 0xa
400 /* Voltage monitor on channel 2*/
401 #define I2C_VOL_MONITOR_ADDR 0x40
402 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
403 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
404 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
406 #define CONFIG_VID_FLS_ENV "ls1046aqds_vdd_mv"
407 #ifndef CONFIG_SPL_BUILD
410 #define CONFIG_VOL_MONITOR_IR36021_SET
411 #define CONFIG_VOL_MONITOR_INA220
412 /* The lowest and highest voltage allowed for LS1046AQDS */
413 #define VDD_MV_MIN 819
414 #define VDD_MV_MAX 1212
417 * Miscellaneous configurable options
420 #define CONFIG_SYS_MEMTEST_START 0x80000000
421 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
423 #define CONFIG_SYS_HZ 1000
425 #define CONFIG_SYS_INIT_SP_OFFSET \
426 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
428 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
433 #define CONFIG_ENV_OVERWRITE
435 #ifdef CONFIG_TFABOOT
436 #define CONFIG_SYS_MMC_ENV_DEV 0
438 #define CONFIG_ENV_SIZE 0x2000
439 #define CONFIG_ENV_OFFSET 0x500000 /* 5MB */
440 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x500000)
441 #define CONFIG_ENV_SECT_SIZE 0x20000
443 #ifdef CONFIG_NAND_BOOT
444 #define CONFIG_ENV_SIZE 0x2000
445 #define CONFIG_ENV_OFFSET (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
446 #elif defined(CONFIG_SD_BOOT)
447 #define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
448 #define CONFIG_SYS_MMC_ENV_DEV 0
449 #define CONFIG_ENV_SIZE 0x2000
450 #elif defined(CONFIG_QSPI_BOOT)
451 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
452 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
453 #define CONFIG_ENV_SECT_SIZE 0x10000
455 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
456 #define CONFIG_ENV_SECT_SIZE 0x20000
457 #define CONFIG_ENV_SIZE 0x20000
461 #define CONFIG_CMDLINE_TAG
463 #undef CONFIG_BOOTCOMMAND
464 #ifdef CONFIG_TFABOOT
465 #define QSPI_NOR_BOOTCOMMAND "sf probe && sf read $kernel_load " \
466 "e0000 f00000 && bootm $kernel_load"
467 #define IFC_NOR_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
468 "$kernel_size && bootm $kernel_load"
469 #define SD_BOOTCOMMAND "mmc info; mmc read $kernel_load" \
470 "$kernel_addr_sd $kernel_size_sd && bootm $kernel_load"
472 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
473 #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \
474 "e0000 f00000 && bootm $kernel_load"
476 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
477 "$kernel_size && bootm $kernel_load"
481 #include <asm/fsl_secure_boot.h>
483 #endif /* __LS1046AQDS_H__ */