1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016 Freescale Semiconductor, Inc.
6 #ifndef __LS1046AQDS_H__
7 #define __LS1046AQDS_H__
9 #include "ls1046a_common.h"
12 unsigned long get_board_sys_clk(void);
15 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
17 #define CONFIG_SKIP_LOWLEVEL_INIT
19 #define CONFIG_LAYERSCAPE_NS_ACCESS
21 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
22 /* Physical Memory Map */
23 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
25 #define SPD_EEPROM_ADDRESS 0x51
26 #define CONFIG_SYS_SPD_BUS_NUM 0
29 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
33 #ifdef CONFIG_FSL_DSPI
34 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */
35 #define CONFIG_SPI_FLASH_SST /* cs1 */
36 #define CONFIG_SPI_FLASH_EON /* cs2 */
39 #ifdef CONFIG_SYS_DPAA_FMAN
40 #define RGMII_PHY1_ADDR 0x1
41 #define RGMII_PHY2_ADDR 0x2
42 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
43 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
44 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
45 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
46 /* PHY address on QSGMII riser card on slot 2 */
47 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
48 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
49 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
50 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
53 #ifdef CONFIG_RAMBOOT_PBL
54 #define CONFIG_SYS_FSL_PBL_PBI \
55 board/freescale/ls1046aqds/ls1046aqds_pbi.cfg
58 #ifdef CONFIG_NAND_BOOT
59 #define CONFIG_SYS_FSL_PBL_RCW \
60 board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg
64 #ifdef CONFIG_SD_BOOT_QSPI
65 #define CONFIG_SYS_FSL_PBL_RCW \
66 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg
68 #define CONFIG_SYS_FSL_PBL_RCW \
69 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg
74 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
75 #define CONFIG_FSL_IFC
77 * CONFIG_SYS_FLASH_BASE has the final address (core view)
78 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
79 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
80 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
82 #define CONFIG_SYS_FLASH_BASE 0x60000000
83 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
84 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
86 #ifdef CONFIG_MTD_NOR_FLASH
87 #define CONFIG_SYS_FLASH_QUIET_TEST
88 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
94 #define CONFIG_LPUART_32B_REG
95 #define CFG_UART_MUX_MASK 0x6
96 #define CFG_UART_MUX_SHIFT 1
97 #define CFG_LPUART_EN 0x2
101 #define CONFIG_SYS_I2C_EEPROM_NXID
102 #define CONFIG_SYS_EEPROM_BUS_NUM 0
107 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
108 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
109 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
110 CSPR_PORT_SIZE_16 | \
113 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
114 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
116 CSPR_PORT_SIZE_16 | \
119 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
121 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
123 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
124 FTIM0_NOR_TEADC(0x5) | \
125 FTIM0_NOR_TAVDS(0x6) | \
126 FTIM0_NOR_TEAHC(0x5))
127 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
128 FTIM1_NOR_TRAD_NOR(0x1a) | \
129 FTIM1_NOR_TSEQRAD_NOR(0x13))
130 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \
131 FTIM2_NOR_TCH(0x8) | \
132 FTIM2_NOR_TWPH(0xe) | \
134 #define CONFIG_SYS_NOR_FTIM3 0
136 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
137 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
138 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
139 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
141 #define CONFIG_SYS_FLASH_EMPTY_INFO
142 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
143 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
145 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
146 #define CONFIG_SYS_WRITE_SWAPPED_DATA
149 * NAND Flash Definitions
151 #define CONFIG_NAND_FSL_IFC
153 #define CONFIG_SYS_NAND_BASE 0x7e800000
154 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
156 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
158 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
162 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
163 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
164 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
165 | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
166 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
167 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
168 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
169 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
171 #define CONFIG_SYS_NAND_ONFI_DETECTION
173 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
174 FTIM0_NAND_TWP(0x18) | \
175 FTIM0_NAND_TWCHT(0x7) | \
177 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
178 FTIM1_NAND_TWBE(0x39) | \
179 FTIM1_NAND_TRR(0xe) | \
180 FTIM1_NAND_TRP(0x18))
181 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
182 FTIM2_NAND_TREH(0xa) | \
183 FTIM2_NAND_TWHRE(0x1e))
184 #define CONFIG_SYS_NAND_FTIM3 0x0
186 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
187 #define CONFIG_SYS_MAX_NAND_DEVICE 1
188 #define CONFIG_MTD_NAND_VERIFY_WRITE
190 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
193 #ifdef CONFIG_NAND_BOOT
194 #define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */
195 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
196 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
199 #if defined(CONFIG_TFABOOT) || \
200 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
201 #define CONFIG_QIXIS_I2C_ACCESS
207 #define CONFIG_FSL_QIXIS
209 #ifdef CONFIG_FSL_QIXIS
210 #define QIXIS_BASE 0x7fb00000
211 #define QIXIS_BASE_PHYS QIXIS_BASE
212 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
213 #define QIXIS_LBMAP_SWITCH 6
214 #define QIXIS_LBMAP_MASK 0x0f
215 #define QIXIS_LBMAP_SHIFT 0
216 #define QIXIS_LBMAP_DFLTBANK 0x00
217 #define QIXIS_LBMAP_ALTBANK 0x04
218 #define QIXIS_LBMAP_NAND 0x09
219 #define QIXIS_LBMAP_SD 0x00
220 #define QIXIS_LBMAP_SD_QSPI 0xff
221 #define QIXIS_LBMAP_QSPI 0xff
222 #define QIXIS_RCW_SRC_NAND 0x110
223 #define QIXIS_RCW_SRC_SD 0x040
224 #define QIXIS_RCW_SRC_QSPI 0x045
225 #define QIXIS_RST_CTL_RESET 0x41
226 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
227 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
228 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
230 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
231 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
235 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
236 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
237 CSOR_NOR_NOR_MODE_AVD_NOR | \
241 * QIXIS Timing parameters for IFC GPCM
243 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
244 FTIM0_GPCM_TEADC(0x20) | \
245 FTIM0_GPCM_TEAHC(0x10))
246 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
247 FTIM1_GPCM_TRAD(0x1f))
248 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
249 FTIM2_GPCM_TCH(0x8) | \
250 FTIM2_GPCM_TWP(0xf0))
251 #define CONFIG_SYS_FPGA_FTIM3 0x0
254 #ifdef CONFIG_TFABOOT
255 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
256 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
257 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
258 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
259 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
260 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
261 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
262 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
263 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
264 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
265 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
266 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
267 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
268 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
269 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
270 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
271 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
272 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
273 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
274 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
275 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
276 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
277 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
278 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
279 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
280 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
281 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
282 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
283 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
284 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
285 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
286 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
288 #ifdef CONFIG_NAND_BOOT
289 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
290 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
291 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
292 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
293 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
294 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
295 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
296 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
297 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
298 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
299 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
300 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
301 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
302 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
303 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
304 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
305 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
306 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
307 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
308 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
309 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
310 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
311 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
312 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
313 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
314 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
315 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
316 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
317 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
318 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
319 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
320 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
322 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
323 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
324 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
325 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
326 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
327 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
328 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
329 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
330 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
331 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
332 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
333 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
334 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
335 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
336 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
337 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
338 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
339 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
340 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
341 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
342 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
343 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
344 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
345 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
346 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
347 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
348 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
349 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
350 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
351 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
352 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
353 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
358 * I2C bus multiplexer
360 #define I2C_MUX_PCA_ADDR_PRI 0x77
361 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
362 #define I2C_RETIMER_ADDR 0x18
363 #define I2C_MUX_CH_DEFAULT 0x8
364 #define I2C_MUX_CH_CH7301 0xC
365 #define I2C_MUX_CH5 0xD
366 #define I2C_MUX_CH6 0xE
367 #define I2C_MUX_CH7 0xF
369 #define I2C_MUX_CH_VOL_MONITOR 0xa
371 /* Voltage monitor on channel 2*/
372 #define I2C_VOL_MONITOR_ADDR 0x40
373 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
374 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
375 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
377 #define CONFIG_VID_FLS_ENV "ls1046aqds_vdd_mv"
378 #ifndef CONFIG_SPL_BUILD
381 #define CONFIG_VOL_MONITOR_IR36021_SET
382 #define CONFIG_VOL_MONITOR_INA220
383 /* The lowest and highest voltage allowed for LS1046AQDS */
384 #define VDD_MV_MIN 819
385 #define VDD_MV_MAX 1212
388 * Miscellaneous configurable options
391 #define CONFIG_SYS_HZ 1000
393 #define CONFIG_SYS_INIT_SP_OFFSET \
394 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
396 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
402 #define CONFIG_CMDLINE_TAG
404 #undef CONFIG_BOOTCOMMAND
405 #ifdef CONFIG_TFABOOT
406 #define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \
407 "env exists secureboot && esbc_halt;;"
408 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd" \
409 "env exists secureboot && esbc_halt;;"
410 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
411 "env exists secureboot && esbc_halt;;"
412 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
413 "env exists secureboot && esbc_halt;;"
415 #if defined(CONFIG_QSPI_BOOT)
416 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
417 "env exists secureboot && esbc_halt;;"
418 #elif defined(CONFIG_NAND_BOOT)
419 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \
420 "env exists secureboot && esbc_halt;;"
421 #elif defined(CONFIG_SD_BOOT)
422 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
423 "env exists secureboot && esbc_halt;;"
425 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
426 "env exists secureboot && esbc_halt;;"
430 #include <asm/fsl_secure_boot.h>
432 #endif /* __LS1046AQDS_H__ */