include/configs/ls1046aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __LS1046AQDS_H__
   7 #define __LS1046AQDS_H__
   8
   9 #include "ls1046a_common.h"
  10
  11 /* Physical Memory Map */
  12
  13 #define SPD_EEPROM_ADDRESS              0x51
  14
  15 #ifdef CONFIG_SYS_DPAA_FMAN
  16 #define RGMII_PHY1_ADDR         0x1
  17 #define RGMII_PHY2_ADDR         0x2
  18 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  19 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  20 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  21 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  22 /* PHY address on QSGMII riser card on slot 2 */
  23 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
  24 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
  25 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
  26 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
  27 #endif
  28
  29 /* IFC */
  30 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  31 /*
  32  * CFG_SYS_FLASH_BASE has the final address (core view)
  33  * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
  34  * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  35  * CONFIG_TEXT_BASE is linked to 0x60000000 for booting
  36  */
  37 #define CFG_SYS_FLASH_BASE                      0x60000000
  38 #define CFG_SYS_FLASH_BASE_PHYS         CFG_SYS_FLASH_BASE
  39 #define CFG_SYS_FLASH_BASE_PHYS_EARLY   0x00000000
  40 #endif
  41
  42 /* LPUART */
  43 #ifdef CONFIG_LPUART
  44 #define CFG_UART_MUX_MASK       0x6
  45 #define CFG_UART_MUX_SHIFT      1
  46 #define CFG_LPUART_EN           0x2
  47 #endif
  48
  49 /*
  50  * IFC Definitions
  51  */
  52 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  53 #define CFG_SYS_NOR0_CSPR_EXT   (0x0)
  54 #define CFG_SYS_NOR0_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
  55                                 CSPR_PORT_SIZE_16 | \
  56                                 CSPR_MSEL_NOR | \
  57                                 CSPR_V)
  58 #define CFG_SYS_NOR1_CSPR_EXT   (0x0)
  59 #define CFG_SYS_NOR1_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \
  60                                 + 0x8000000) | \
  61                                 CSPR_PORT_SIZE_16 | \
  62                                 CSPR_MSEL_NOR | \
  63                                 CSPR_V)
  64 #define CFG_SYS_NOR_AMASK               IFC_AMASK(128 * 1024 * 1024)
  65
  66 #define CFG_SYS_NOR_CSOR                (CSOR_NOR_ADM_SHIFT(4) | \
  67                                         CSOR_NOR_TRHZ_80)
  68 #define CFG_SYS_NOR_FTIM0               (FTIM0_NOR_TACSE(0x4) | \
  69                                         FTIM0_NOR_TEADC(0x5) | \
  70                                         FTIM0_NOR_TAVDS(0x6) | \
  71                                         FTIM0_NOR_TEAHC(0x5))
  72 #define CFG_SYS_NOR_FTIM1               (FTIM1_NOR_TACO(0x35) | \
  73                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
  74                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
  75 #define CFG_SYS_NOR_FTIM2               (FTIM2_NOR_TCS(0x8) | \
  76                                         FTIM2_NOR_TCH(0x8) | \
  77                                         FTIM2_NOR_TWPH(0xe) | \
  78                                         FTIM2_NOR_TWP(0x1c))
  79 #define CFG_SYS_NOR_FTIM3               0
  80
  81 #define CFG_SYS_FLASH_BANKS_LIST        {CFG_SYS_FLASH_BASE_PHYS, \
  82                                         CFG_SYS_FLASH_BASE_PHYS + 0x8000000}
  83
  84 #define CFG_SYS_WRITE_SWAPPED_DATA
  85
  86 /*
  87  * NAND Flash Definitions
  88  */
  89
  90 #define CFG_SYS_NAND_BASE               0x7e800000
  91 #define CFG_SYS_NAND_BASE_PHYS  CFG_SYS_NAND_BASE
  92
  93 #define CFG_SYS_NAND_CSPR_EXT   (0x0)
  94
  95 #define CFG_SYS_NAND_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
  96                                 | CSPR_PORT_SIZE_8      \
  97                                 | CSPR_MSEL_NAND        \
  98                                 | CSPR_V)
  99 #define CFG_SYS_NAND_AMASK      IFC_AMASK(64*1024)
 100 #define CFG_SYS_NAND_CSOR       (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 101                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 102                                 | CSOR_NAND_ECC_MODE_8  /* 8-bit ECC */ \
 103                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 104                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 105                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 106                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 107
 108 #define CFG_SYS_NAND_FTIM0              (FTIM0_NAND_TCCST(0x7) | \
 109                                         FTIM0_NAND_TWP(0x18)   | \
 110                                         FTIM0_NAND_TWCHT(0x7) | \
 111                                         FTIM0_NAND_TWH(0xa))
 112 #define CFG_SYS_NAND_FTIM1              (FTIM1_NAND_TADLE(0x32) | \
 113                                         FTIM1_NAND_TWBE(0x39)  | \
 114                                         FTIM1_NAND_TRR(0xe)   | \
 115                                         FTIM1_NAND_TRP(0x18))
 116 #define CFG_SYS_NAND_FTIM2              (FTIM2_NAND_TRAD(0xf) | \
 117                                         FTIM2_NAND_TREH(0xa) | \
 118                                         FTIM2_NAND_TWHRE(0x1e))
 119 #define CFG_SYS_NAND_FTIM3           0x0
 120
 121 #define CFG_SYS_NAND_BASE_LIST  { CFG_SYS_NAND_BASE }
 122 #endif
 123
 124 #ifdef CONFIG_NAND_BOOT
 125 #define CFG_SYS_NAND_U_BOOT_SIZE        (768 << 10)
 126 #endif
 127
 128 #if defined(CONFIG_TFABOOT) || \
 129         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 130 #endif
 131
 132 /*
 133  * QIXIS Definitions
 134  */
 135
 136 #ifdef CONFIG_FSL_QIXIS
 137 #define QIXIS_BASE                      0x7fb00000
 138 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 139 #define CFG_SYS_I2C_FPGA_ADDR   0x66
 140 #define QIXIS_LBMAP_SWITCH              6
 141 #define QIXIS_LBMAP_MASK                0x0f
 142 #define QIXIS_LBMAP_SHIFT               0
 143 #define QIXIS_LBMAP_DFLTBANK            0x00
 144 #define QIXIS_LBMAP_ALTBANK             0x04
 145 #define QIXIS_LBMAP_NAND                0x09
 146 #define QIXIS_LBMAP_SD                  0x00
 147 #define QIXIS_LBMAP_SD_QSPI             0xff
 148 #define QIXIS_LBMAP_QSPI                0xff
 149 #define QIXIS_RCW_SRC_NAND              0x110
 150 #define QIXIS_RCW_SRC_SD                0x040
 151 #define QIXIS_RCW_SRC_QSPI              0x045
 152 #define QIXIS_RST_CTL_RESET             0x41
 153 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 154 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 155 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 156
 157 #define CFG_SYS_FPGA_CSPR_EXT   (0x0)
 158 #define CFG_SYS_FPGA_CSPR               (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 159                                         CSPR_PORT_SIZE_8 | \
 160                                         CSPR_MSEL_GPCM | \
 161                                         CSPR_V)
 162 #define CFG_SYS_FPGA_AMASK              IFC_AMASK(64 * 1024)
 163 #define CFG_SYS_FPGA_CSOR               (CSOR_NOR_ADM_SHIFT(4) | \
 164                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 165                                         CSOR_NOR_TRHZ_80)
 166
 167 /*
 168  * QIXIS Timing parameters for IFC GPCM
 169  */
 170 #define CFG_SYS_FPGA_FTIM0              (FTIM0_GPCM_TACSE(0xc) | \
 171                                         FTIM0_GPCM_TEADC(0x20) | \
 172                                         FTIM0_GPCM_TEAHC(0x10))
 173 #define CFG_SYS_FPGA_FTIM1              (FTIM1_GPCM_TACO(0x50) | \
 174                                         FTIM1_GPCM_TRAD(0x1f))
 175 #define CFG_SYS_FPGA_FTIM2              (FTIM2_GPCM_TCS(0x8) | \
 176                                         FTIM2_GPCM_TCH(0x8) | \
 177                                         FTIM2_GPCM_TWP(0xf0))
 178 #define CFG_SYS_FPGA_FTIM3              0x0
 179 #endif
 180
 181 #ifdef CONFIG_TFABOOT
 182 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NOR0_CSPR_EXT
 183 #define CFG_SYS_CSPR0           CFG_SYS_NOR0_CSPR
 184 #define CFG_SYS_AMASK0          CFG_SYS_NOR_AMASK
 185 #define CFG_SYS_CSOR0           CFG_SYS_NOR_CSOR
 186 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NOR_FTIM0
 187 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NOR_FTIM1
 188 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NOR_FTIM2
 189 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NOR_FTIM3
 190 #define CFG_SYS_CSPR1_EXT               CFG_SYS_NOR1_CSPR_EXT
 191 #define CFG_SYS_CSPR1           CFG_SYS_NOR1_CSPR
 192 #define CFG_SYS_AMASK1          CFG_SYS_NOR_AMASK
 193 #define CFG_SYS_CSOR1           CFG_SYS_NOR_CSOR
 194 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NOR_FTIM0
 195 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NOR_FTIM1
 196 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NOR_FTIM2
 197 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NOR_FTIM3
 198 #define CFG_SYS_CSPR2_EXT               CFG_SYS_NAND_CSPR_EXT
 199 #define CFG_SYS_CSPR2           CFG_SYS_NAND_CSPR
 200 #define CFG_SYS_AMASK2          CFG_SYS_NAND_AMASK
 201 #define CFG_SYS_CSOR2           CFG_SYS_NAND_CSOR
 202 #define CFG_SYS_CS2_FTIM0               CFG_SYS_NAND_FTIM0
 203 #define CFG_SYS_CS2_FTIM1               CFG_SYS_NAND_FTIM1
 204 #define CFG_SYS_CS2_FTIM2               CFG_SYS_NAND_FTIM2
 205 #define CFG_SYS_CS2_FTIM3               CFG_SYS_NAND_FTIM3
 206 #define CFG_SYS_CSPR3_EXT               CFG_SYS_FPGA_CSPR_EXT
 207 #define CFG_SYS_CSPR3           CFG_SYS_FPGA_CSPR
 208 #define CFG_SYS_AMASK3          CFG_SYS_FPGA_AMASK
 209 #define CFG_SYS_CSOR3           CFG_SYS_FPGA_CSOR
 210 #define CFG_SYS_CS3_FTIM0               CFG_SYS_FPGA_FTIM0
 211 #define CFG_SYS_CS3_FTIM1               CFG_SYS_FPGA_FTIM1
 212 #define CFG_SYS_CS3_FTIM2               CFG_SYS_FPGA_FTIM2
 213 #define CFG_SYS_CS3_FTIM3               CFG_SYS_FPGA_FTIM3
 214 #else
 215 #ifdef CONFIG_NAND_BOOT
 216 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NAND_CSPR_EXT
 217 #define CFG_SYS_CSPR0           CFG_SYS_NAND_CSPR
 218 #define CFG_SYS_AMASK0          CFG_SYS_NAND_AMASK
 219 #define CFG_SYS_CSOR0           CFG_SYS_NAND_CSOR
 220 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NAND_FTIM0
 221 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NAND_FTIM1
 222 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NAND_FTIM2
 223 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NAND_FTIM3
 224 #define CFG_SYS_CSPR1_EXT               CFG_SYS_NOR0_CSPR_EXT
 225 #define CFG_SYS_CSPR1           CFG_SYS_NOR0_CSPR
 226 #define CFG_SYS_AMASK1          CFG_SYS_NOR_AMASK
 227 #define CFG_SYS_CSOR1           CFG_SYS_NOR_CSOR
 228 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NOR_FTIM0
 229 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NOR_FTIM1
 230 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NOR_FTIM2
 231 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NOR_FTIM3
 232 #define CFG_SYS_CSPR2_EXT               CFG_SYS_NOR1_CSPR_EXT
 233 #define CFG_SYS_CSPR2           CFG_SYS_NOR1_CSPR
 234 #define CFG_SYS_AMASK2          CFG_SYS_NOR_AMASK
 235 #define CFG_SYS_CSOR2           CFG_SYS_NOR_CSOR
 236 #define CFG_SYS_CS2_FTIM0               CFG_SYS_NOR_FTIM0
 237 #define CFG_SYS_CS2_FTIM1               CFG_SYS_NOR_FTIM1
 238 #define CFG_SYS_CS2_FTIM2               CFG_SYS_NOR_FTIM2
 239 #define CFG_SYS_CS2_FTIM3               CFG_SYS_NOR_FTIM3
 240 #define CFG_SYS_CSPR3_EXT               CFG_SYS_FPGA_CSPR_EXT
 241 #define CFG_SYS_CSPR3           CFG_SYS_FPGA_CSPR
 242 #define CFG_SYS_AMASK3          CFG_SYS_FPGA_AMASK
 243 #define CFG_SYS_CSOR3           CFG_SYS_FPGA_CSOR
 244 #define CFG_SYS_CS3_FTIM0               CFG_SYS_FPGA_FTIM0
 245 #define CFG_SYS_CS3_FTIM1               CFG_SYS_FPGA_FTIM1
 246 #define CFG_SYS_CS3_FTIM2               CFG_SYS_FPGA_FTIM2
 247 #define CFG_SYS_CS3_FTIM3               CFG_SYS_FPGA_FTIM3
 248 #else
 249 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NOR0_CSPR_EXT
 250 #define CFG_SYS_CSPR0           CFG_SYS_NOR0_CSPR
 251 #define CFG_SYS_AMASK0          CFG_SYS_NOR_AMASK
 252 #define CFG_SYS_CSOR0           CFG_SYS_NOR_CSOR
 253 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NOR_FTIM0
 254 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NOR_FTIM1
 255 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NOR_FTIM2
 256 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NOR_FTIM3
 257 #define CFG_SYS_CSPR1_EXT               CFG_SYS_NOR1_CSPR_EXT
 258 #define CFG_SYS_CSPR1           CFG_SYS_NOR1_CSPR
 259 #define CFG_SYS_AMASK1          CFG_SYS_NOR_AMASK
 260 #define CFG_SYS_CSOR1           CFG_SYS_NOR_CSOR
 261 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NOR_FTIM0
 262 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NOR_FTIM1
 263 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NOR_FTIM2
 264 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NOR_FTIM3
 265 #define CFG_SYS_CSPR2_EXT               CFG_SYS_NAND_CSPR_EXT
 266 #define CFG_SYS_CSPR2           CFG_SYS_NAND_CSPR
 267 #define CFG_SYS_AMASK2          CFG_SYS_NAND_AMASK
 268 #define CFG_SYS_CSOR2           CFG_SYS_NAND_CSOR
 269 #define CFG_SYS_CS2_FTIM0               CFG_SYS_NAND_FTIM0
 270 #define CFG_SYS_CS2_FTIM1               CFG_SYS_NAND_FTIM1
 271 #define CFG_SYS_CS2_FTIM2               CFG_SYS_NAND_FTIM2
 272 #define CFG_SYS_CS2_FTIM3               CFG_SYS_NAND_FTIM3
 273 #define CFG_SYS_CSPR3_EXT               CFG_SYS_FPGA_CSPR_EXT
 274 #define CFG_SYS_CSPR3           CFG_SYS_FPGA_CSPR
 275 #define CFG_SYS_AMASK3          CFG_SYS_FPGA_AMASK
 276 #define CFG_SYS_CSOR3           CFG_SYS_FPGA_CSOR
 277 #define CFG_SYS_CS3_FTIM0               CFG_SYS_FPGA_FTIM0
 278 #define CFG_SYS_CS3_FTIM1               CFG_SYS_FPGA_FTIM1
 279 #define CFG_SYS_CS3_FTIM2               CFG_SYS_FPGA_FTIM2
 280 #define CFG_SYS_CS3_FTIM3               CFG_SYS_FPGA_FTIM3
 281 #endif
 282 #endif
 283
 284 /*
 285  * I2C bus multiplexer
 286  */
 287 #define I2C_MUX_PCA_ADDR_PRI            0x77
 288 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 289 #define I2C_RETIMER_ADDR                0x18
 290 #define I2C_MUX_CH_DEFAULT              0x8
 291 #define I2C_MUX_CH_CH7301               0xC
 292 #define I2C_MUX_CH5                     0xD
 293 #define I2C_MUX_CH6                     0xE
 294 #define I2C_MUX_CH7                     0xF
 295
 296 #define I2C_MUX_CH_VOL_MONITOR 0xa
 297
 298 /* Voltage monitor on channel 2*/
 299 #define I2C_VOL_MONITOR_ADDR           0x40
 300 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 301 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 302 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 303
 304 /* The lowest and highest voltage allowed for LS1046AQDS */
 305 #define VDD_MV_MIN                      819
 306 #define VDD_MV_MAX                      1212
 307
 308 /*
 309  * Miscellaneous configurable options
 310  */
 311
 312 /*
 313  * Environment
 314  */
 315
 316 #ifdef CONFIG_TFABOOT
 317 #define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; "   \
 318                            "env exists secureboot && esbc_halt;;"
 319 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd"      \
 320                            "env exists secureboot && esbc_halt;;"
 321 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "     \
 322                            "env exists secureboot && esbc_halt;;"
 323 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "   \
 324                            "env exists secureboot && esbc_halt;;"
 325 #endif
 326
 327 #include <asm/fsl_secure_boot.h>
 328
 329 #endif /* __LS1046AQDS_H__ */