1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016 Freescale Semiconductor, Inc.
6 #ifndef __LS1046AQDS_H__
7 #define __LS1046AQDS_H__
9 #include "ls1046a_common.h"
11 #define CONFIG_LAYERSCAPE_NS_ACCESS
13 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
14 /* Physical Memory Map */
16 #define SPD_EEPROM_ADDRESS 0x51
17 #define CONFIG_SYS_SPD_BUS_NUM 0
20 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
23 #ifdef CONFIG_SYS_DPAA_FMAN
24 #define RGMII_PHY1_ADDR 0x1
25 #define RGMII_PHY2_ADDR 0x2
26 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
27 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
28 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
29 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
30 /* PHY address on QSGMII riser card on slot 2 */
31 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
32 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
33 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
34 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
38 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
40 * CONFIG_SYS_FLASH_BASE has the final address (core view)
41 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
42 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
43 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
45 #define CONFIG_SYS_FLASH_BASE 0x60000000
46 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
47 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
49 #ifdef CONFIG_MTD_NOR_FLASH
50 #define CONFIG_SYS_FLASH_QUIET_TEST
51 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
57 #define CONFIG_LPUART_32B_REG
58 #define CFG_UART_MUX_MASK 0x6
59 #define CFG_UART_MUX_SHIFT 1
60 #define CFG_LPUART_EN 0x2
64 #define CONFIG_SYS_I2C_EEPROM_NXID
65 #define CONFIG_SYS_EEPROM_BUS_NUM 0
70 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
71 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
72 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
76 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
77 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
82 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
84 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
86 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
87 FTIM0_NOR_TEADC(0x5) | \
88 FTIM0_NOR_TAVDS(0x6) | \
90 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
91 FTIM1_NOR_TRAD_NOR(0x1a) | \
92 FTIM1_NOR_TSEQRAD_NOR(0x13))
93 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \
94 FTIM2_NOR_TCH(0x8) | \
95 FTIM2_NOR_TWPH(0xe) | \
97 #define CONFIG_SYS_NOR_FTIM3 0
99 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
100 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
101 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
103 #define CONFIG_SYS_FLASH_EMPTY_INFO
104 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
105 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
107 #define CONFIG_SYS_WRITE_SWAPPED_DATA
110 * NAND Flash Definitions
113 #define CONFIG_SYS_NAND_BASE 0x7e800000
114 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
116 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
118 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
122 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
123 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
124 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
125 | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
126 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
127 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
128 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
129 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
131 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
132 FTIM0_NAND_TWP(0x18) | \
133 FTIM0_NAND_TWCHT(0x7) | \
135 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
136 FTIM1_NAND_TWBE(0x39) | \
137 FTIM1_NAND_TRR(0xe) | \
138 FTIM1_NAND_TRP(0x18))
139 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
140 FTIM2_NAND_TREH(0xa) | \
141 FTIM2_NAND_TWHRE(0x1e))
142 #define CONFIG_SYS_NAND_FTIM3 0x0
144 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
145 #define CONFIG_SYS_MAX_NAND_DEVICE 1
146 #define CONFIG_MTD_NAND_VERIFY_WRITE
149 #ifdef CONFIG_NAND_BOOT
150 #define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */
151 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
154 #if defined(CONFIG_TFABOOT) || \
155 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
156 #define CONFIG_QIXIS_I2C_ACCESS
162 #define CONFIG_FSL_QIXIS
164 #ifdef CONFIG_FSL_QIXIS
165 #define QIXIS_BASE 0x7fb00000
166 #define QIXIS_BASE_PHYS QIXIS_BASE
167 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
168 #define QIXIS_LBMAP_SWITCH 6
169 #define QIXIS_LBMAP_MASK 0x0f
170 #define QIXIS_LBMAP_SHIFT 0
171 #define QIXIS_LBMAP_DFLTBANK 0x00
172 #define QIXIS_LBMAP_ALTBANK 0x04
173 #define QIXIS_LBMAP_NAND 0x09
174 #define QIXIS_LBMAP_SD 0x00
175 #define QIXIS_LBMAP_SD_QSPI 0xff
176 #define QIXIS_LBMAP_QSPI 0xff
177 #define QIXIS_RCW_SRC_NAND 0x110
178 #define QIXIS_RCW_SRC_SD 0x040
179 #define QIXIS_RCW_SRC_QSPI 0x045
180 #define QIXIS_RST_CTL_RESET 0x41
181 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
182 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
183 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
185 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
186 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
190 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
191 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
192 CSOR_NOR_NOR_MODE_AVD_NOR | \
196 * QIXIS Timing parameters for IFC GPCM
198 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
199 FTIM0_GPCM_TEADC(0x20) | \
200 FTIM0_GPCM_TEAHC(0x10))
201 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
202 FTIM1_GPCM_TRAD(0x1f))
203 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
204 FTIM2_GPCM_TCH(0x8) | \
205 FTIM2_GPCM_TWP(0xf0))
206 #define CONFIG_SYS_FPGA_FTIM3 0x0
209 #ifdef CONFIG_TFABOOT
210 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
211 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
212 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
213 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
214 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
215 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
216 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
217 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
218 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
219 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
220 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
221 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
222 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
223 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
224 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
225 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
226 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
227 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
228 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
229 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
230 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
231 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
232 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
233 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
234 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
235 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
236 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
237 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
238 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
239 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
240 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
241 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
243 #ifdef CONFIG_NAND_BOOT
244 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
245 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
246 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
247 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
248 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
249 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
250 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
251 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
252 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
253 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
254 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
255 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
256 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
257 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
258 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
259 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
260 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
261 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
262 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
263 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
264 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
265 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
266 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
267 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
268 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
269 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
270 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
271 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
272 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
273 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
274 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
275 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
277 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
278 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
279 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
280 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
281 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
282 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
283 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
284 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
285 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
286 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
287 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
288 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
289 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
290 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
291 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
292 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
293 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
294 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
295 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
296 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
297 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
298 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
299 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
300 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
301 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
302 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
303 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
304 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
305 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
306 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
307 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
308 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
313 * I2C bus multiplexer
315 #define I2C_MUX_PCA_ADDR_PRI 0x77
316 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
317 #define I2C_RETIMER_ADDR 0x18
318 #define I2C_MUX_CH_DEFAULT 0x8
319 #define I2C_MUX_CH_CH7301 0xC
320 #define I2C_MUX_CH5 0xD
321 #define I2C_MUX_CH6 0xE
322 #define I2C_MUX_CH7 0xF
324 #define I2C_MUX_CH_VOL_MONITOR 0xa
326 /* Voltage monitor on channel 2*/
327 #define I2C_VOL_MONITOR_ADDR 0x40
328 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
329 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
330 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
332 /* The lowest and highest voltage allowed for LS1046AQDS */
333 #define VDD_MV_MIN 819
334 #define VDD_MV_MAX 1212
337 * Miscellaneous configurable options
340 #define CONFIG_SYS_INIT_SP_OFFSET \
341 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
343 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
349 #ifdef CONFIG_TFABOOT
350 #define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \
351 "env exists secureboot && esbc_halt;;"
352 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd" \
353 "env exists secureboot && esbc_halt;;"
354 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
355 "env exists secureboot && esbc_halt;;"
356 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
357 "env exists secureboot && esbc_halt;;"
360 #include <asm/fsl_secure_boot.h>
362 #endif /* __LS1046AQDS_H__ */