include/configs/ls1046aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __LS1046AQDS_H__
   7 #define __LS1046AQDS_H__
   8
   9 #include "ls1046a_common.h"
  10
  11 #define CONFIG_LAYERSCAPE_NS_ACCESS
  12
  13 /* Physical Memory Map */
  14
  15 #define SPD_EEPROM_ADDRESS              0x51
  16
  17 #ifdef CONFIG_DDR_ECC
  18 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  19 #endif
  20
  21 #ifdef CONFIG_SYS_DPAA_FMAN
  22 #define RGMII_PHY1_ADDR         0x1
  23 #define RGMII_PHY2_ADDR         0x2
  24 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  25 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  26 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  27 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  28 /* PHY address on QSGMII riser card on slot 2 */
  29 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
  30 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
  31 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
  32 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
  33 #endif
  34
  35 /* IFC */
  36 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  37 /*
  38  * CONFIG_SYS_FLASH_BASE has the final address (core view)
  39  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
  40  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  41  * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
  42  */
  43 #define CONFIG_SYS_FLASH_BASE                   0x60000000
  44 #define CONFIG_SYS_FLASH_BASE_PHYS              CONFIG_SYS_FLASH_BASE
  45 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY        0x00000000
  46
  47 #ifdef CONFIG_MTD_NOR_FLASH
  48 #define CONFIG_SYS_FLASH_QUIET_TEST
  49 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
  50 #endif
  51 #endif
  52
  53 /* LPUART */
  54 #ifdef CONFIG_LPUART
  55 #define CFG_UART_MUX_MASK       0x6
  56 #define CFG_UART_MUX_SHIFT      1
  57 #define CFG_LPUART_EN           0x2
  58 #endif
  59
  60 /* EEPROM */
  61 #define CONFIG_SYS_I2C_EEPROM_NXID
  62 #define CONFIG_SYS_EEPROM_BUS_NUM               0
  63
  64 /*
  65  * IFC Definitions
  66  */
  67 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  68 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  69 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  70                                 CSPR_PORT_SIZE_16 | \
  71                                 CSPR_MSEL_NOR | \
  72                                 CSPR_V)
  73 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
  74 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  75                                 + 0x8000000) | \
  76                                 CSPR_PORT_SIZE_16 | \
  77                                 CSPR_MSEL_NOR | \
  78                                 CSPR_V)
  79 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  80
  81 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  82                                         CSOR_NOR_TRHZ_80)
  83 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
  84                                         FTIM0_NOR_TEADC(0x5) | \
  85                                         FTIM0_NOR_TAVDS(0x6) | \
  86                                         FTIM0_NOR_TEAHC(0x5))
  87 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
  88                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
  89                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
  90 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x8) | \
  91                                         FTIM2_NOR_TCH(0x8) | \
  92                                         FTIM2_NOR_TWPH(0xe) | \
  93                                         FTIM2_NOR_TWP(0x1c))
  94 #define CONFIG_SYS_NOR_FTIM3            0
  95
  96 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  97 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  98 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  99
 100 #define CONFIG_SYS_FLASH_EMPTY_INFO
 101 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 102                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 103
 104 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 105
 106 /*
 107  * NAND Flash Definitions
 108  */
 109
 110 #define CONFIG_SYS_NAND_BASE            0x7e800000
 111 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 112
 113 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 114
 115 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 116                                 | CSPR_PORT_SIZE_8      \
 117                                 | CSPR_MSEL_NAND        \
 118                                 | CSPR_V)
 119 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 120 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 121                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 122                                 | CSOR_NAND_ECC_MODE_8  /* 8-bit ECC */ \
 123                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 124                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 125                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 126                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 127
 128 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 129                                         FTIM0_NAND_TWP(0x18)   | \
 130                                         FTIM0_NAND_TWCHT(0x7) | \
 131                                         FTIM0_NAND_TWH(0xa))
 132 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 133                                         FTIM1_NAND_TWBE(0x39)  | \
 134                                         FTIM1_NAND_TRR(0xe)   | \
 135                                         FTIM1_NAND_TRP(0x18))
 136 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 137                                         FTIM2_NAND_TREH(0xa) | \
 138                                         FTIM2_NAND_TWHRE(0x1e))
 139 #define CONFIG_SYS_NAND_FTIM3           0x0
 140
 141 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 142 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 143 #define CONFIG_MTD_NAND_VERIFY_WRITE
 144 #endif
 145
 146 #ifdef CONFIG_NAND_BOOT
 147 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
 148 #endif
 149
 150 #if defined(CONFIG_TFABOOT) || \
 151         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 152 #endif
 153
 154 /*
 155  * QIXIS Definitions
 156  */
 157
 158 #ifdef CONFIG_FSL_QIXIS
 159 #define QIXIS_BASE                      0x7fb00000
 160 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 161 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 162 #define QIXIS_LBMAP_SWITCH              6
 163 #define QIXIS_LBMAP_MASK                0x0f
 164 #define QIXIS_LBMAP_SHIFT               0
 165 #define QIXIS_LBMAP_DFLTBANK            0x00
 166 #define QIXIS_LBMAP_ALTBANK             0x04
 167 #define QIXIS_LBMAP_NAND                0x09
 168 #define QIXIS_LBMAP_SD                  0x00
 169 #define QIXIS_LBMAP_SD_QSPI             0xff
 170 #define QIXIS_LBMAP_QSPI                0xff
 171 #define QIXIS_RCW_SRC_NAND              0x110
 172 #define QIXIS_RCW_SRC_SD                0x040
 173 #define QIXIS_RCW_SRC_QSPI              0x045
 174 #define QIXIS_RST_CTL_RESET             0x41
 175 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 176 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 177 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 178
 179 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 180 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 181                                         CSPR_PORT_SIZE_8 | \
 182                                         CSPR_MSEL_GPCM | \
 183                                         CSPR_V)
 184 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 185 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 186                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 187                                         CSOR_NOR_TRHZ_80)
 188
 189 /*
 190  * QIXIS Timing parameters for IFC GPCM
 191  */
 192 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xc) | \
 193                                         FTIM0_GPCM_TEADC(0x20) | \
 194                                         FTIM0_GPCM_TEAHC(0x10))
 195 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0x50) | \
 196                                         FTIM1_GPCM_TRAD(0x1f))
 197 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0x8) | \
 198                                         FTIM2_GPCM_TCH(0x8) | \
 199                                         FTIM2_GPCM_TWP(0xf0))
 200 #define CONFIG_SYS_FPGA_FTIM3           0x0
 201 #endif
 202
 203 #ifdef CONFIG_TFABOOT
 204 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 205 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 206 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 207 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 208 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 209 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 210 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 211 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 212 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 213 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 214 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 215 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 216 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 217 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 218 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 219 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 220 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 221 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 222 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 223 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 224 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 225 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 226 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 227 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 228 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 229 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 230 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 231 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 232 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 233 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 234 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 235 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 236 #else
 237 #ifdef CONFIG_NAND_BOOT
 238 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 239 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 240 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 241 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 242 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 243 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 244 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 245 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 246 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 247 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 248 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 249 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 250 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 251 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 252 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 253 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 254 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 255 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 256 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 257 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 258 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 259 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 260 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 261 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 262 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 263 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 264 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 265 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 266 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 267 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 268 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 269 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 270 #else
 271 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 272 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 273 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 274 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 275 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 276 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 277 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 278 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 279 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 280 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 281 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 282 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 283 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 284 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 285 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 286 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 287 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 288 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 289 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 290 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 291 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 292 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 293 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 294 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 295 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 296 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 297 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 298 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 299 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 300 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 301 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 302 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 303 #endif
 304 #endif
 305
 306 /*
 307  * I2C bus multiplexer
 308  */
 309 #define I2C_MUX_PCA_ADDR_PRI            0x77
 310 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 311 #define I2C_RETIMER_ADDR                0x18
 312 #define I2C_MUX_CH_DEFAULT              0x8
 313 #define I2C_MUX_CH_CH7301               0xC
 314 #define I2C_MUX_CH5                     0xD
 315 #define I2C_MUX_CH6                     0xE
 316 #define I2C_MUX_CH7                     0xF
 317
 318 #define I2C_MUX_CH_VOL_MONITOR 0xa
 319
 320 /* Voltage monitor on channel 2*/
 321 #define I2C_VOL_MONITOR_ADDR           0x40
 322 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 323 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 324 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 325
 326 /* The lowest and highest voltage allowed for LS1046AQDS */
 327 #define VDD_MV_MIN                      819
 328 #define VDD_MV_MAX                      1212
 329
 330 /*
 331  * Miscellaneous configurable options
 332  */
 333
 334 /*
 335  * Environment
 336  */
 337
 338 #ifdef CONFIG_TFABOOT
 339 #define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; "   \
 340                            "env exists secureboot && esbc_halt;;"
 341 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd"      \
 342                            "env exists secureboot && esbc_halt;;"
 343 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "     \
 344                            "env exists secureboot && esbc_halt;;"
 345 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "   \
 346                            "env exists secureboot && esbc_halt;;"
 347 #endif
 348
 349 #include <asm/fsl_secure_boot.h>
 350
 351 #endif /* __LS1046AQDS_H__ */