Convert CONFIG_SYS_I2C_EEPROM_CCID et al to Kconfig
[platform/kernel/u-boot.git] / include / configs / ls1046afrwy.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2019-2020 NXP
4  */
5
6 #ifndef __LS1046AFRWY_H__
7 #define __LS1046AFRWY_H__
8
9 #include "ls1046a_common.h"
10
11 #define CONFIG_SYS_UBOOT_BASE           0x40100000
12
13 /*
14  * NAND Flash Definitions
15  */
16
17 #define CONFIG_SYS_NAND_BASE            0x7e800000
18 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
19
20 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
21 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
22                                 | CSPR_PORT_SIZE_8      \
23                                 | CSPR_MSEL_NAND        \
24                                 | CSPR_V)
25 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
26 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
27                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
28                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
29                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
30                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
31                                 | CSOR_NAND_SPRZ_128    /* Spare size = 128 */ \
32                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
33
34 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
35                                         FTIM0_NAND_TWP(0x18)   | \
36                                         FTIM0_NAND_TWCHT(0x7) | \
37                                         FTIM0_NAND_TWH(0xa))
38 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
39                                         FTIM1_NAND_TWBE(0x39)  | \
40                                         FTIM1_NAND_TRR(0xe)   | \
41                                         FTIM1_NAND_TRP(0x18))
42 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
43                                         FTIM2_NAND_TREH(0xa) | \
44                                         FTIM2_NAND_TWHRE(0x1e))
45 #define CONFIG_SYS_NAND_FTIM3           0x0
46
47 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
48 #define CONFIG_SYS_MAX_NAND_DEVICE      1
49 #define CONFIG_MTD_NAND_VERIFY_WRITE
50
51 /* IFC Timing Params */
52 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
53 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
54 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
55 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
56 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
57 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
58 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
59 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
60
61 /* EEPROM */
62 #define I2C_RETIMER_ADDR                        0x18
63
64 /* I2C bus multiplexer */
65 #define I2C_MUX_PCA_ADDR_PRI                    0x77 /* Primary Mux*/
66 #define I2C_MUX_CH_DEFAULT                      0x1 /* Channel 0*/
67 #define I2C_MUX_CH_RTC                          0x1 /* Channel 0*/
68
69 /* RTC */
70 #define RTC
71 #define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 0 I2C bus 0*/
72 #define CONFIG_SYS_RTC_BUS_NUM                  0
73
74 /*
75  * Environment
76  */
77 #define CONFIG_SYS_FSL_QSPI_BASE        0x40000000
78
79 #undef BOOT_TARGET_DEVICES
80 #define BOOT_TARGET_DEVICES(func) \
81         func(MMC, mmc, 0) \
82         func(USB, usb, 0) \
83         func(DHCP, dhcp, na)
84
85 /* FMan */
86 #ifdef CONFIG_SYS_DPAA_FMAN
87
88 #define QSGMII_PORT1_PHY_ADDR           0x1c
89 #define QSGMII_PORT2_PHY_ADDR           0x1d
90 #define QSGMII_PORT3_PHY_ADDR           0x1e
91 #define QSGMII_PORT4_PHY_ADDR           0x1f
92
93 #define FDT_SEQ_MACADDR_FROM_ENV
94
95 #endif
96
97 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "   \
98                            "env exists secureboot && esbc_halt;;"
99 #define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; "    \
100                            "env exists secureboot && esbc_halt;"
101
102 #include <asm/fsl_secure_boot.h>
103
104 #endif /* __LS1046AFRWY_H__ */