include/configs/ls1046afrwy.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2019-2020 NXP
   4  */
   5
   6 #ifndef __LS1046AFRWY_H__
   7 #define __LS1046AFRWY_H__
   8
   9 #include "ls1046a_common.h"
  10
  11 #define CONFIG_LAYERSCAPE_NS_ACCESS
  12
  13 #define CONFIG_SYS_UBOOT_BASE           0x40100000
  14
  15 /*
  16  * NAND Flash Definitions
  17  */
  18
  19 #define CONFIG_SYS_NAND_BASE            0x7e800000
  20 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
  21
  22 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  23 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  24                                 | CSPR_PORT_SIZE_8      \
  25                                 | CSPR_MSEL_NAND        \
  26                                 | CSPR_V)
  27 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
  28 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  29                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  30                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
  31                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
  32                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
  33                                 | CSOR_NAND_SPRZ_128    /* Spare size = 128 */ \
  34                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
  35
  36 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
  37                                         FTIM0_NAND_TWP(0x18)   | \
  38                                         FTIM0_NAND_TWCHT(0x7) | \
  39                                         FTIM0_NAND_TWH(0xa))
  40 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
  41                                         FTIM1_NAND_TWBE(0x39)  | \
  42                                         FTIM1_NAND_TRR(0xe)   | \
  43                                         FTIM1_NAND_TRP(0x18))
  44 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
  45                                         FTIM2_NAND_TREH(0xa) | \
  46                                         FTIM2_NAND_TWHRE(0x1e))
  47 #define CONFIG_SYS_NAND_FTIM3           0x0
  48
  49 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
  50 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  51 #define CONFIG_MTD_NAND_VERIFY_WRITE
  52
  53 /* IFC Timing Params */
  54 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
  55 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
  56 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
  57 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
  58 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
  59 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
  60 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
  61 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
  62
  63 /* EEPROM */
  64 #define CONFIG_SYS_I2C_EEPROM_NXID
  65 #define CONFIG_SYS_EEPROM_BUS_NUM               0
  66 #define I2C_RETIMER_ADDR                        0x18
  67
  68 /* I2C bus multiplexer */
  69 #define I2C_MUX_PCA_ADDR_PRI                    0x77 /* Primary Mux*/
  70 #define I2C_MUX_CH_DEFAULT                      0x1 /* Channel 0*/
  71 #define I2C_MUX_CH_RTC                          0x1 /* Channel 0*/
  72
  73 /* RTC */
  74 #define RTC
  75 #define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 0 I2C bus 0*/
  76 #define CONFIG_SYS_RTC_BUS_NUM                  0
  77
  78 /*
  79  * Environment
  80  */
  81 #define CONFIG_SYS_FSL_QSPI_BASE        0x40000000
  82
  83 #ifndef CONFIG_SPL_BUILD
  84 #undef BOOT_TARGET_DEVICES
  85 #define BOOT_TARGET_DEVICES(func) \
  86         func(MMC, mmc, 0) \
  87         func(USB, usb, 0) \
  88         func(DHCP, dhcp, na)
  89 #endif
  90
  91 /* FMan */
  92 #ifdef CONFIG_SYS_DPAA_FMAN
  93
  94 #define QSGMII_PORT1_PHY_ADDR           0x1c
  95 #define QSGMII_PORT2_PHY_ADDR           0x1d
  96 #define QSGMII_PORT3_PHY_ADDR           0x1e
  97 #define QSGMII_PORT4_PHY_ADDR           0x1f
  98
  99 #define FDT_SEQ_MACADDR_FROM_ENV
 100
 101 #endif
 102
 103 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "   \
 104                            "env exists secureboot && esbc_halt;;"
 105 #define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; "    \
 106                            "env exists secureboot && esbc_halt;"
 107
 108 #include <asm/fsl_secure_boot.h>
 109
 110 #endif /* __LS1046AFRWY_H__ */